• 전자공학회논문지D
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• 제34D권10호
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• pp.14-23
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• 1997

An MMIC downconverting mixer for cellular phone application has been successfully developed using an MMIC process including $1 \mu\textrm{m}$ ion implanted gaAs MESFET and passive lumped elements consisting of spiral inductor, $Si_3N_4$ MIM capacitor and NiCr resistor. The configuration of the mixer presented in this paper is single-ended dual-gate FET mixer with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit is $1.4 mm \times 1.03 mm $ including all input matching circuits and a mixing circuit. The conversion gian and noise figure of the mixer at LO powr of 0 dBm are 5.5dB and 19dB, respectively. The two-tone IM3 characteristics are also measured, showing -60dBc at RF power of -30dBm. Allisolations between each port show better than 20dB.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.252-257
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• 1998

Two-stage power factor correction (PFC) converter with a single PWM controller for universal input voltage (90-264V) is proposed. It consists of a power factor pre-regulator cascaded by a DC/DC converter as in a conventional two-stage approach. However, a single PWM controller is used as in a single-stage, single-switch PFC approach. The switch in the PFC part is synchronized with the switch in the DC/DC converter with a fixed switching frequency. Employing an adaptive delay scheme the switch in the PFC part is controlled to limit the energy storage capacitor voltage within a designed range for the optimum efficiency, and to reduce input current harmonic distortion. The experimental results obtained on a 200W (5V/40A) prototype PFC converter are given to verify the effectiveness of the proposed control method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.143-151
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• 2010

In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1537-1543
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• 2014

This paper presents a new DC/AC multilevel converter. This configuration uses single DC sources. The proposed converter has two stages. The first stage is a DC/DC converter that can produce several DC-links in the output. The DC/DC converter is one type of boost converter and uses single inductor. The second stage is a multilevel inverter with several capacitor links. In this paper, one single input multi output DC-DC converter is used in order to voltage balancing on multilevel converter. In addition, as compare to traditional multilevel inverter, presented DC/AC multilevel converter has less on-state voltage drop and conduction losses. Finally, in order to verify the theoretical issues, simulation and experimental results are presented.

• 전기전자학회논문지
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• 제28권1호
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• pp.78-89
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• 2024

차량용 반도체에서 사용되는 BCD 공정 기반의 PMIC 칩은 아날로그 회로를 트리밍하기 위해 추가 마스크가 필요없는 MTP(Multi-Time Programmable) IP(Intellectual Property)를 요구한다. 본 논문에서는 저면적 MTP IP 설계를 위해 2개의 트랜지스터와 1개의 MOS 커패시터를 갖는 single poly EEPROM 셀인 MTP 셀에서 NCAP(NMOS Capacitor) 대신 PCAP(PMOS Capacitor)을 사용한 MTP 셀을 사용하여 MTP 셀 사이즈를 18.4% 정도 줄였다. 그리고 MTP IP 회로 설계 관점에서 MTP IP 설계의 CG 구동회로와 TG 구동회로에 2-stage voltage shifter 회로를 적용하였고, DC-DC 변환기 회로의 면적을 줄이기 위해 전하 펌핑 방식을 사용하는 VPP(=7.75V), VNN(=-7.75V)와 VNNL(=-2.5V) 전하 펌프 회로에서 각각의 전하 펌프마다 별도로 두고 있는 ring oscillator 회로를 하나만 둔 회로를 제안하였으며, VPPL(=2.5V)은 전하펌프 대신 voltage regulator 회로를 사용하는 방식을 제안하였다. 180nm BCD 공정 기반으로 설계된 4Kb MTP IP 사이즈는 0.493mm²이다.

• 한국막학회:학술대회논문집
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• 한국막학회 1995년도 제3회 심포지움 (분리막 연구의 최신동향)
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• pp.57-71
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• 1995

A simple mathematical model for gacilitated mass transport with a fixed site carrier membrane was derived by assuming an instantaneous, microscopic concentration (activity) fluctuation, The concentration fluctuation, developed due to reversible chemical reaction between carrier and solute, could acuse the higher chemical potential gradient and the facilitated transport. For mathematical formulation, an analogy was employed between the mass transfer for the facilitated transport with fixed site carrier membrane and the electron transfer in a parallel resistor-capacitor (RC) circuit. For the single RC model, it was assumed that a single capacitor represented the total carrier and a solute could not inter-diffuse between matrix and carrier, allowing only two diffusional pathways, This assumption was relaxed by adopting a serial combination of the parallel RC circuit. Here, a solute diffuses in two elements (matrix or carrier) can exchange its pathway, exhibiting four diffusional pathways. The current models were examined against experimental data and the agreement was exceptional.

• 대한전자공학회논문지SD
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• 제44권2호
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• pp.25-33
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• 2007

본 논문에서는 높은 dynamic range(DR)를 얻을 수 있는 단일-비트 4차 델타-시그마 모듈레이터를 제시하였으며, 이를 구현하였다. 본 모듈레이터에 사용된 루프 필터의 구조는 피드백 패스와 피드포워드 패스를 혼합하여 사용한 구조이며, 스위치-커패시터(switched-capacitor) 방식으로 구현되었다. 측정 결과로는 20kHz의 기저대역(base band)에서 3.2MHz의 클록을 사용하였을 때 최대 99dB의 DR을 얻었다. 본 모듈레이터는 $0.18{\mu}m$ standard CMOS 공정으로 만들어졌다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제50권11호
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• pp.568-574
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• 2001

This paper describes a current fed high frequency resonant inverter can be used as the power supply for wax-sealing. This circuit configuration is composed of conventional two unit inverter of single ended current find type in parallel. The proposed inverter can realize ZVS operation by using resonant capacitor to ZVS capacitor and has merits not only reduction of switch current distribution but also extension of load range in comparison with the conventional single-ended current fed high frequency resonant inverter. This analysis of proposed circuit uses normalized parameter and characteristic estimation which is needed in each step before design is generally described according to normalized frequency($\mu$), normalized resistance(λ) and parameters. On the basis of characteristic values, a method of the circuit design is presented. Also, the theoretical analysis is proved through experiment and this proposed circuit shows that it can be practically used as the power supply system for wax-sealing and DC-DC converter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.451-462
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• 2016

Photovoltaic energy conversion becomes main focus of many researches due to its promising potential as source for future electricity and has many advantages than the other alternative energy sources like wind, solar, ocean, biomass, geothermal etc. In Photovoltaic power generation multilevel inverters play a vital role in power conversion. The three different topologies, diode-clamped (neutral-point clamped) inverter, capacitor-clamped (flying capacitor) inverter and cascaded h-bridge multilevel inverter are widely used in these multilevel inverters. Among the three topologies, cascaded h-bridge multilevel inverter is more suitable for photovoltaic applications since each pv array can act as a separate dc source for each h-bridge module. This paper presents a single phase Cascaded H-bridge five level inverter for grid-connected photovoltaic application using sinusoidal pulse width modulation technique. This inverter output voltage waveform reduces the harmonics in the generated current and the filtering effort at the input. The control strategy allows the independent control of each dc-link voltages and tracks the maximum power point of PV strings. This topology can inject to the grid sinusoidal input currents with unity power factor and achieves low harmonic distortion. A PID control algorithm is implemented in Arm Processor LPC2148. The validity of the proposed inverter is verified through simulation and is implemented in a single phase 100W prototype. The results of hardware are compared with simulation results. The proposed system offers improved performance over conventional three level inverter in terms of THD.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.207-209
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• 2019

This paper proposes a grid-tied photovoltaic (PV) system, consisting of Voltage-fed dual-active-bridge (DAB) dc-dc converter with single phase inverter. The proposed converter allows a small dc-link capacitor, so that system reliability can be improved by replacing electrolytic capacitors with film capacitors. The double line frequency free maximum power point tracking (MPPT) is also realized in the proposed converter by using Ripple Correlation method. First of all, to eliminate the double line frequency ripple which influence the reduction of DC source capacitance, control is developed. Then, a designing of Current control in DQ frame is analyzed and to fulfill the international harmonics standards such as IEEE 519 and P1547, $3^{rd}$ harmonic in the grid is directly compensated by the feedforward terms generated by the PR controller with the grid current in stationary frame to achieve desire Total Harmonic Distortion (THD). 5-kW PV converter and inverter module with a small dc-link film capacitor was built in the laboratory with the proposed control and MPPT algorithm. Experimental results are given to validate the converter performance.