• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.464-469
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• 2005

Optimum sensitivity analysis (OSA) is the process to find the sensitivity of optimum solution with respect to the parameter in the optimization problem. The prevalent OSA methods calculate the optimum sensitivity as a post-processing. In this research, a simple technique is proposed to obtain optimum sensitivity as a result of the original optimization problem, provided that the optimum sensitivity of objective function is required. The parameters are considered as additional design variables in the original optimization problem. And then, it is endowed with equality constraints to penalize the additional variables. When the optimization problem is solved, the optimum sensitivity of objective function is simultaneously obtained as Lagrange multiplier. Several mathematical and engineering examples are solved to show the applicability and efficiency of the method compared to other OSA ones.

• Bulletin of the Korean Mathematical Society
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• v.31 no.2
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• pp.167-172
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• 1994

For a given $C^{*}$-dynamical system (A, G, .alpha.) with a G-simple $C^{*}$-algebra A (that is A has no proper .alpha.-invariant ideal) many authors have studied the simplicity of a $C^{*}$-crossed product A $x_{\alpha{r}}$ G. In [1] topological freeness of an action is shown to guarantee the simplicity of the reduced $C^{*}$-crossed product A $x_{\alpha{r}}$ G when A is G-simple. In this paper we investigate the pure infiniteness of a simple $C^{*}$-crossed product A $x_{\alpha}$ G of a purely infinite simple $C^{*}$-algebra A and a topologically free action .alpha. of a finite group G, and find a sufficient condition in terms of the action on the spectrum of the multiplier algebra M(A) of A. Showing this we also prove that some extension of a topologically free action is still topologically free.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.26-33
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• 2002

In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.

• Journal of the Korea Society of Computer and Information
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• v.17 no.3
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• pp.1-10
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• 2012

A low-complexity Multiplication over GF(2m) and multiplier circuit has been proposed by using cyclic-shift coefficients and the irreducible trinomial. The proposed circuit has the parallel input/output architecture and shows the lower-complexity than others with the characteristics of the cyclic-shift coefficients and the irreducible trinomial modular computation. The proposed multiplier is composed of $2m^2$ 2-input AND gates and m (m+2) 2-input XOR gates without the memories and switches. And the minimum propagation delay is $T_A+(2+{\lceil}log_2m{\rceil})T_X$. The Proposed circuit architecture is well suited to VLSI implementation because it is simple, regular and modular.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

• Journal of Convergence for Information Technology
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• v.9 no.5
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• pp.7-13
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• 2019

Role-based access or attribute-based access control in cloud environment or big data environment need requires a suitable mathematical structure to represent a hierarchical model. This paper define the notion of multipliers and simple multipliers of lattice implication algebras that can implement a hierarchical model of role-based or attribute-based access control, and prove every multiplier is simple multiplier. Also we research the relationship between multipliers and homomorphisms of a lattice implication algebra L, and prove that the lattice [0, u] is isomorphic to a lattice $[u^{\prime},1]$ for each $u{\in}L$ and that L is isomorphic to $[u,1]{\times}[u^{\prime},1]$ as lattice implication algebras for each $u{\in}L$ satisfying $u{\vee}u^{\prime}=1$.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1030-1033
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• 2002

This paper, a new simple controller operates in continuous conduction mode (CCM) for Boost power factor collection converter is introduced. The duty ratios are obtained by comparisons of a sensed signal from inductor current and a negative ramp carrier waveform in each switching period. By using the proposed controller, input voltage sensing, error amplifier in the current feedback loop, and analog multiplier／divider are not required, then, the control circuit implementation is very simple. To verify the proposed controller, the circuit simulation for Boost power factor correction converter was applied. For the results, the input current waveform was shaped to be closely sinusoidal, implying low THD.

• Bulletin of the Korean Mathematical Society
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• v.50 no.3
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• pp.915-928
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• 2013

In this paper, we will provide an alternative proof to characterize the pointwise multipliers which maps a Sobolev space $\dot{H}^r(\mathb{R}^d)$ to its dual $\dot{H}^{-r}(\mathb{R}^d)$ in the case 0 < $r$ < $\frac{d}{2}$ by a simple application of the definition of fractional Sobolev space. The proof relies on a method introduced by Maz'ya-Verbitsky [9] to prove the same result.

• Journal of IKEEE
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• v.26 no.4
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• pp.736-741
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• 2022

Lattice-based cryptography is the most practical post-quantum cryptography because it enjoys strong worst-case security, relatively efficient implementation, and simplicity. Ring learning with errors (R-LWE) is a public key encryption (PKE) method of lattice-based encryption (LBC), and the most important operation of R-LWE is the modular polynomial multiplication of rings. This paper proposes a method for optimizing modular multipliers based on approximate computing (AC) technology, targeting the medium-security parameter set of the R-LWE cryptosystem. First, as a simple way to implement complex logic, LUT is used to omit some of the approximate multiplication operations, and the 2's complement method is used to calculate the number of bits whose value is 1 when converting the value of the input data to binary. We propose a total of two methods to reduce the number of required adders by minimizing them. The proposed LUT-based modular multiplier reduced both speed and area by 9% compared to the existing R-LWE modular multiplier, and the modular multiplier using the 2's complement method reduced the area by 40% and improved the speed by 2%. appear. Finally, the area of the optimized modular multiplier with both of these methods applied was reduced by up to 43% compared to the previous one, and the speed was reduced by up to 10%.

• Journal of Ocean Engineering and Technology
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• v.25 no.4
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• pp.36-41
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• 2011

In the present paper, a direct forcing/fictitious domain (DF/FD) level set method is proposed to simulate the FSI (fluid-solid interaction) in two-phase flow. The main idea is to combine the direct-forcing/fictitious domain (DF/FD) method with the level set method in the Cartesian coordinates. The DF/FD method is a non-Lagrange-multiplier version of a distributed Lagrange multiplier/fictitious domain (DLM/FD) method. This method does not sacrifice the accuracy and robustness by employing a discrete ${\delta}$ (Dirac delta) function to transfer quantities between the Eulerian nodes and Lagrangian points explicitly as the immersed boundary method. The advantages of this approach are the simple concept, easy implementation, and utilization of the original governing equation without modification. Simulations of various water-entry problems have been conducted to validate the capability and accuracy of the present method in solving the FSI in two-phase flow. Consequently, the present results are found to be in good agreement with those of previous studies.