• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.47-51
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• 2000

A modified direct bonding technique employing a wet chemical deposition of $SiO_2$ film on a wafer surface to be bonded is proposed for the fabrication of Si-$SiO_2$-Si structures. Structural and electrical quality of the bonded wafers is studied. Satisfied insulating properties of interfacial $SiO_2$ layers are demonstrated. Elastic strain caused by surface morphology is investigated. The diminution of strain in the grooved structures is semi-quantitatively interpreted by a model considering the virtual defects distributed over the interfacial region.

• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.29-32
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• 2004

Fully depleted Silicon-on-Insulator (FD-SOI) devices lead to better electrical characteristics than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO2 layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three-dimensional (3-D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3-D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3-D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller that a critical value in a finger-type layout. The current degradation fro the 3-D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.448-452
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• 2004

The micromachined variable optical attenuator(VOA) was presented in the paper. The VOA has two single mode fiber(SMF) aligned with free space and symmetric parallel plate actuator with microshutter, which can control a amount of light by driving the actuator. In the paper, analysis on driving performances of the VOA was performed and can be reduced threshold voltage through the decreasing displacement actuating range. This paper presents a VOA that is fabricated using bosch deep silicon etching process with silicon on insulator(SOD wafer. The VOA consists of driving electrode, ground electrode, actuating microshutter, and mechanical stopper. In this VOA, actuating shutter is driven by electrostatic force and the threshold voltage is close to 28V, 46V come along with the spring width of 5${\mu}{\textrm}{m}$, 7${\mu}{\textrm}{m}$ respectively. Attenuation range is measured from 2.4㏈ to 16.7㏈.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.21-22
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• 2005

Partially-depleted Silicon on insulator metal-oxide-semiconductor field- effect transistors (PD-SOI MOSFETs) with Silicon-germanium (SiGe) layer is investigated. This structure uses SiGe layer to reduce the kink effect in the floating body region near the bottom channel/buried oxide interface. Among many design parameters influencing the performance of the device, Ge composition is presented most predominant effects, simulation results show that kink effect is reduced with increase the Ge composition. Because the bandgap of SiGe layer is reduced at higher Ge composition, the hole current between body and SiGe layer is enhanced.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.11
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• pp.939-942
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• 2007

We investigated the characteristics of UTB-SOI pMOSFETs with SOI thickness($T_{SOI}$) ranging from 10 nm to 1 nm and evaluated the dependence of electrical characteristics on the silicon surface orientation. As a result, it is found that the subthreshold characteristics of (100)-surface UTB-SOI pMOSFETs were superior to (110)-surface. However, the hole mobility of (110)-surface were larger than that of (100)-surface. Especially, the enhancement of effective hole mobility at the effective field of 0.1 MV/cm was observed from 3-nm to 5-nm SOI thickness range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.33-33
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• 2009

Silicon nano-structures have great potential in bionic sensor applications. Atomic force microscopy (AFM) anodic oxidation have many advantages for the nanostructure fabrication, such as simple process in atmosphere at room temperature, compatibility with conventional Si process. In this work, we fabricated simple FET structures with channel width W~ 10nm (nanowire) and $1{\mu}m$ (nano-ribbon) on ~10, 20 and 100nm-thinned silicon-on-insulator (SOI) wafers in order to investigate the surface effect on the transport characteristics of nano-channel. For further quantitative analysis, we carried out the 2D numerical simulations to investigate the effect of channel surface states on the carrier distribution behavior inside the channel. The simulated 2D cross-sectional structures of fabricated devices had channel heights of H ~ 10, 20, and 100nm, widths of L ~ $1{\mu}m$ and 10nm respectively, where we simultaneously varied the channel surface charge density from $1{\times}10^{-9}$ to $1{\times}10^{-7}C/cm2$. It has been shown that the side-wall charge of nanowire channel mainly affect the I-V characteristics and this was confirmed by the 2D numerical simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.223-226
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• 2003

The EKV model, a continuous model for the MOS transistor, has been adapted to both partially depleted SOI MOSFETs with grounded body (GBSOI) and dynamic threshold MOS (DTMOS) transistors. Adaptation is straightforward and helps to understand the physics of the DTMOS. Excellent agreement is found between the model and the measured characteristics of GBSOI and DTMOS devices

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.283-284
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• 2012

In this work, a special technique called dielectric filling was carried out in order to reduce sub-threshold leakage current inside double-gated n-channel MOSFET. This calibration was done by using SILVACO Atlas(TCAD), and the result showed quite a good performance compared to the conventional double-gate MOSFET.

• Proceedings of the Optical Society of Korea Conference
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• 2003.07a
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• pp.230-231
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• 2003

SOI (Silicon On insulator)는 SiO$_2$와 같은 절연체 위에 실리콘 (Si) 박막층이 놓여있는 구조로서 전자나 광소자들이 실리콘 박막층 위에 만들어진다. SOI의 기본적인 생각은 기생 정전용량 (parasitic capacitance)을 감소시킴으로서 소자의 스위칭 속도를 더 빠르게 하는 것이다. 최근에 초고속 광소자와 단위 광소자들의 집적을 위해 실리콘 이외의 GaAs, InP, SiC 등의 반도체 박막을 절연층 위에 만드는 연구가 많이 진행되고있다. (중략)

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.729-732
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• 2006

The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.