• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.118-119
• /
• 2009

This paper presents the feature profile evolution silicon deep trench etching, which is very crucial for the commercial wafer process application. The silicon deep trenches were etched with the SF6 gas & Hbr gas based process recipe. The optimized silicon deep trench process resulted in vertical profiles (87o~90o) with loading effect of < 1%. The process recipes were developed for the silicon deep trench etching applications. This scheme provides vertically profiles without notching of top corner was observed. In this study, the production of SF6 gas based silicon deep trench etch process much more strongly than expected on the basis of Hbr gas trench process that have been investigated by scanning electron microscope (SEM). Based on the test results, it is concluded that the silicon deep trench etching shows the sufficient profile for practical MOS FET silicon deep trench technology process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.19-20
• /
• 2006

Two methods that can reduce reflectance in solar cells are surface texturing and anti-reflection coating. Wet chemical etching is a typical method that surface texturing of multi-crystalline silicon. Wet chemical etching methods are the acid texturization of saw damage on the surface of multi-crystalline silicon or double-step chemical etching after KOH saw damage removal too. These methods of surface texturing are realized by chemical etching in acid solutions HF-$HNO_3$-$H_2O$. In this solutions we can reduce reflectance spectra by simple process etching of multi-crystalline silicon surface. We have obtained reflectance of 27.19% m 400~1100nm from acidic chemical etching after KOH saw damage removal. This result is about 7% less than just saw damage removal substrate. The surface morphology observed by microscope and scanning electron microscopy (SEM).

• Journal of the Korean Vacuum Society
• /
• v.6 no.3
• /
• pp.242-248
• /
• 1997

Porous silicons were prepared by dry etching as well as by chemical etching. The latter is a conventional method used by many researchers. Meanwhile, the former is a new method we developed. Also the porous silicon structure was made by E-beam lithography technique. However, due to the limit of this technique, minimum size we could produce was about 0.3 $\mu\textrm{m}$ in diameter on silicon wafer. In a new method, the porous silicon microstructure was fabricated by using Reactive Ion Etching method after covering with diamond powder on 4 inch wafer by using spin coater. In this method, diamond powder acted as a mask. The morphology of samples prepared under many different conditions were analysed be SEM and AFM. And we measured PL spectra for the samples. Based on these results, we observed the structure of a few hundreds $\AA$ in size from porous silicon which was made by dry etching with diamond powder. Also the PL peak for these samples lied around 590 nm compared to 760 nm for chemically etched porous silicon.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.12
• /
• pp.2221-2225
• /
• 2007

Hollow-type microneedle array can be used for painless, continuous and stable drug delivery through a human skin. The needles must be sharp and have sufficient length in order to penetrate the epidermis. An array of hollow-type silicon microneedles was fabricated by using deep reactive ion etching and HNA wet etching with two oxide masks. Isotropic etching was used to create tapered tips of the needles, and anisotropic etching of Bosch process was used to make the extended length and holes of microneedles. The microneedles were formed by three steps of isotropic, anisotropic, and isotropic etching in order. The holes were made by one anisotropic etching step. The fabricated microneedles have $170{\mu}m$ width, $40{\mu}m$ hole diameter and $230{\mu}m$ length.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.12
• /
• pp.1106-1110
• /
• 2005

We fabricated (110) silicon hard master by using anisotropic wet etching for embossing. The etching chemical for the silicon wafer was a TMAH $25\%$ solution. The anisotropic wet etching produces a smooth sidewall surface and the surface roughness of the fabricated master is about 3 nm. After spin coating an organic-inorganic sol-gel hybrid material on a silicon substrate, we employed hot embossing technique operated at a low pressure and temperature to form patterns on the silicon substrate by using the fabricated master. We successfully fabricated the multi-mode planar optical waveguides showing low propagation loss of 0.4 dB/cm. The surface roughness of embossed patterns was uniform for more than 10 times of the embossing processes with a single hydrophobic surface treatment of the silicon hard master.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.6
• /
• pp.312-316
• /
• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.237-240
• /
• 2001

In this paper, we have presented processing technique about wet etching for silicon membrane construction formation. In order to make selective etching of backside silicon wafer, we used Si$_3$N$_4$ layer by PECVD(Plasma Enhanced Chemical Vapor Deposition). We have measured the surface thickness in backside silicon wafer after anisortropic wet etching with KOH:distilled water solutions. Through this experiment, we acquired the etching rate for 1.29${\mu}{\textrm}{m}$/min. The average rough of Si-membrane frontside and backside was 0.26${\mu}{\textrm}{m}$, 0.90${\mu}{\textrm}{m}$, respectively.

• Journal of Integrative Natural Science
• /
• v.6 no.3
• /
• pp.170-175
• /
• 2013

Silicon nanowires were detached and obtained from silicon nanowire arrays on silicon substrate using a ultrasono-method. Silicon nanowire arrays on silicon substrate were prepared with an electroless metal assisted etching of p-type silicon. The etching solution was an aqueous HF solution containing silver nitrate. SEM observation shows that well-aligned nanowire arrays perpendicular to the surface of the silicon substrate were produced. After sonication of silicon nanowire array, an individual silicon nanowire was confirmed by FESEM. Optical characteristics of SiNWs were measured by FT-IR spectroscopy. The surface of SiNWs are terminated with hydrogen.

• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.1
• /
• pp.23-27
• /
• 2011

Fabrication of porous silicon(PS) double layer by electrochemical etching is the first step in process of ultrathin solar cell using PS layer transfer process. The porosity of the porous silicon layer can be controlled by regulating the formation parameters such as current density and HF concentration. PS layer is fabricated by electrochemical etching in a chemical mixture of HF and ethanol. For electrochemical etching, highly boron doped (100) oriented monocrystalline Si substrates was used. Ths resistivity of silicon is $0.01-0.02\;{\Omega}{\cdot}cm$. The solution composition for electrochemical etching was HF (40%) : $C_2H_5OH$(99 %) : $H_2O$ = 1 : 1 : 2 (by volume). In order to fabricate porous silicon double layer, current density was switched. By switching current density from low to high level, a high-porosity layer was fabricated beneath a low-porosity layer. Etching time affects only the depth of porous silicon layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.7
• /
• pp.616-621
• /
• 2009

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating(ARC) and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si ARC layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layers were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The structure of porous Si layers was investigated with SEM. The formation of a nanoporous Si layer about 100nm thick on the textured silicon wafer result in a reflectance lower than 5% in the wavelength region from 500 to 900nm. Such a surface modification allows improving the Si solar cell characteristics. An efficiency of 13.4% is achieved on a monocrystalline silicon solar cell using the electrochemical technique.