• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.196-198
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• 2007

A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.

• Journal of Sensor Science and Technology
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• v.21 no.2
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• pp.121-126
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• 2012

Piezoresistive type contact force sensor array is fabricated by (111) Silicon bulk micromachining for continuous blood pressure monitoring. Length and width of the unit sensor structure is $200{\mu}m$ and $190{\mu}m$, respectively. The gap between sensing elements is only $10{\mu}m$. To achieve wafer level packaging, the sensor structure is capped by PDMS soft cap using wafer molding and bonding process with $10{\mu}m$ alignment precision. The resistance change over contact force was measured to verify the feasibility of the proposed sensor scheme. The maximum measurement range and resolution is 900 mm Hg and 0.57 mm Hg, respectively.

• Current Applied Physics
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• v.18 no.11
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• pp.1436-1440
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• 2018

SiN and SiCN film production using plasma-enhanced atomic layer deposition (PE-ALD) is investigated in this study. A developed high-power and high-density multiple inductively coupled plasma (multi-ICP) source is used for a low temperature PE-ALD process. High plasma density and good uniformity are obtained by high power $N_2$ plasma discharge. Silicon nitride films are deposited on a 300-mm wafer using the PE-ALD method at low temperature. To analyze the quality of the SiN and SiCN films, the wet etch rate, refractive index, and growth rate of the thin films are measured. Experiments are performed by changing the applied power and the process temperature ($300-500^{\circ}C$).

• Journal of Adhesion and Interface
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• v.24 no.2
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• pp.60-63
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• 2023

The AlGaN/GaN heterostructure has high electron mobility due to the two-dimensional electron gas (2-DEG) layer, and has the characteristic of high breakdown voltage at high temperature due to its wide bandgap, making it a promising candidate for high-power and high-frequency electronic devices. Despite these advantages, there are factors that affect the reliability of various device properties such as current collapse. To address this issue, this paper used metal-organic chemical vapor deposition to continuously deposit AlGaN/GaN heterostructure and SiN passivation layer. Material and electrical properties of GaN HEMTs with/without SiN cap layer were analyzed, and based on the results, low-frequency noise characteristics of GaN HEMTs were measured to analyze the conduction mechanism model and the cause of defects within the channel.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.538-539
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• 2013

여러 장점으로 인해 OLED는 디스플레이 및 조명 등 적용분야가 넓어지고 있지만, 수분 및 산소에 취약하여 그 수명이 제한되는 단점이 있다. 이를 해결하고자 현재까지는 glass cap을 이용한 encapsulation 기술이 적용되고 있지만, flexible 기판에 적용하지 못하는 문제가 있다. 이러한 문제를 해결하고자 여러 가지 thin film encapsulation 기술이 적용되고 있으나 보다 신뢰성이 높은 기술의 개발이 절실한 때이다. Encapsulation 무기 박막 물질로서 $Si_3N_4$ 박막은 PE-CVD (Plasma Enhanced Chemical Vapor Deposition) 등의 박막 증착법을 사용한 많은 연구가 진행되어, 저온에서의 좋은 품질의 박막 증착이 가능하지만, 100도 이하의 thermal budget을 갖는 OLED Encapsulation에 사용하기에는 충분하지 않았다. CVD 박막의 특성을 더욱 개선하기 위해 최근 ALD (Atomic Layer Deposition) 방법을 통한 $Al_2O_3$ film 증착 방법이 연구되고 있지만, 낮은 증착 속도로 인해 양산에 걸림돌이 되고 있다. 본 연구에서는 또 다른 해결책으로서 Digital CVD 방법을 이용한 양질의 $Si_3N_4$ 박막의 증착을 연구하였다. 이것은 ALD 증착법과 유사하며, 1st step에서 PECVD 방법으로 4~5 ${\AA}$의 얇은 silicon 박막을 증착하고, 2nd step에서 nitrogen plasma를 이용하여 질화 반응을 진행하고, 이러한 cycle을 원하는 두께가 될 때까지 반복적으로 진행된다. 이 때 1 cycle 당 증착속도는 7 ${\AA}$/cycle 정도였다. 최적의 증착 방법과 조건으로 기존의 CVD $Si_3N_4$ 박막 대비 1/5 이하로 pinhole을 최소화 할 수는 있지만 완벽하게 제거하기는 힘든 문제가 있고, 이를 해결하기 위한 개선을 위한 접근 방법이 필요하다고 판단하였다. 본 연구에서는 무기물 박막인 carbon nitride를 이용한 SiN/C:N multilayer 증착 연구를 진행하였다. Fig. 1은 CVD 조건으로 증착된 두께 750 nm SiN film에서 여러 층의 C:N film layer를 삽입했을 때, 38 시간의 85%/$85^{\circ}C$ 가속실험에 따라 OLED의 발광 사진이다. 그림에서 볼 수 있듯이 C:N 층을 삽입하고 또한 그 박막의 수가 증가함에 따라서 OLED에 대한 encapsulation 특성이 크게 개선됨을 확인할 수 있다.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.30-36
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• 2020

We demonstrated a successful fabrication of 4" Gallium Nitride (GaN)/Diamond High Electron Mobility Transistors (HEMTs) incorporated with Inner Slot Via Hole process. We made in manufacturing technology of 4" GaN/Diamond HEMT wafers in a compound semiconductor foundry since reported [1]. Wafer thickness uniformity and wafer flatness of starting GaN/Diamond wafers have improved greatly, which contributed to improved processing yield. By optimizing Laser drilling techniques, we successfully demonstrated a through-substrate-via process, which is last hurdle in GaN/Diamond manufacturing technology. To fully exploit Diamond's superior thermal property for GaN HEMT devices, we include Aluminum Nitride (AlN) barrier in epitaxial layer structure, in addition to conventional Aluminum Gallium Nitride (AlGaN) barrier layer. The current collapse revealed very stable up to Vds = 90 V. The trapping behaviors were measured Emission Microscope (EMMI). The traps are located in interface between Silicon Nitride (SiN) passivation layer and GaN cap layer.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1504-1507
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• 1999

We have grown vertically aligned carbon nanotubes in a large area of Co-Ni codeposited Si substrates by the thermal CVD using $C_2H_2$ gas. Since the discovery of carbon nanotubes, Synthesis of carbon nanotubes for mass production has been achieved by several methods such as laser vaporization arc discharge, and pyrolysis. In particular, growth of vertically aligned nanotubes is of technological importance for applications to FED. Recently, vertically aligned carbon nanotubes have been grown on glass by PECVD Aligned carbon nanotubes can be also grown on mesoporous silica and Fe patterned porous silicon using CVD. Despite such breakthroughs in the growth, the growth mechanism of the alignment are still far from being clearly understood. Furthermore, FED has not been clearly demonstrated yet at a practical level. Here, we demonstrate that carbon nanotubes can be vertically aligned on catalyzed Si substrate when the domain density reaches a certain value. We suggest that steric hindrance between nanotubes at an initial stage of the growth forces nanotubes to align vertically and then nanotubes are further grown by the cap growth mechanism.

• Journal of IKEEE
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• v.13 no.4
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• pp.23-27
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• 2009

Ohmic contact formation and etching processes for the fabrication of MBE (molecular beam epitaxy) grown GaSb-based p-channel HEMT devices on Si substrate have been studied. Firstly, mesa etching process was established for device isolation, based on both HF-based wet etching and ICP-based dry etching. Ohmic contact process for the source and drain formation was also studied based on Ge/Au/Ni/Au metal stack, which resulted in a contact resistance as low as $0.683\;{\Omega}mm$ with RTA at $320^{\circ}C$ for 60s. Finally, for gate formation of HEMT device, gate recess process was studied based on AZ300 developer and citric acid-based wet etching, in which the latter turned out to have high etching selectivity between GaSb and AlGaSb layers that were used as the cap and the barrier of the device, respectively.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.9-18
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• 1998

A single RF transceiver chip for an extended GSM handset application was designedm, fabricated and evaluated. A RFIC was fabricated by using silicon BiCMOS process, and then packaged in 80 pin TQFP of $10 {\times} 10 mm^{2}$ in size. As a result, it was achieved guite reasonable integraty and good RF performance at the operation voltage of 3.3V. This paper describes development results of RF receiver section of the RFIC, which includes LNA, down conversion mixer, AGC, switched capacitor filter and down sampling mixer. The test results show that RF receiver section is well operated within frequency range of 925 ~960 MHz, which is defined on the extended GSM specification (E-GSM). The receiver section also reveals moderate power consumption of 67 mA and minimum detectable signal of -105 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.32-38
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• 2011

This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18${\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is $1.1{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.0{\times}0.4mm^2$. Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.