• ETRI Journal
• /
• v.35 no.1
• /
• pp.158-161
• /
• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• Proceedings of the KIEE Conference
• /
• 1987.07b
• /
• pp.1583-1586
• /
• 1987

In the study for effective speech control we designed a personal computer system with A/D converter in which the speech signal is transformed by digital data displayed graphically on the moniter and with a D/A converter in which the digital data is transformed into speech signal which people can hear. We analyzed the character of the speech signal produced by the system. We designed the adaptive noise cancel algorithm so that noise and Interference are cancelled whenever the speech signal is recognized by the computer system. This is a basic system for artificial Intelligence.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.34S no.6
• /
• pp.67-76
• /
• 1997

In radar signal processing, an A/D converter with sufficient dynamic range and high sampling speed is required to detect the weakest target signals in heavy clutter and ECM environments. As the sampling frequency increases, the amount of digital data transfered to the signal processing module is also increased. To overcome these massive data transfer burden, we need an A/D conversion module with an enough data transfer rate. In this paper, we proposed an implementation scheme of a new A/D conversio module that can be used in multi-mode 3-D phased array radar signal processing system, and evaluated the performance. The proposed A/D conversion module is implemented with a standard A/D converter and a 6U-standard VME bus.

• Journal of Sensor Science and Technology
• /
• v.16 no.3
• /
• pp.187-191
• /
• 2007

This paper presents a development of the multi-channel data acquisition/logging system for a sensor signal processing and a method of the evaluation and a temperature compensation for the A/D converters with the specific analog and digital circuit including the software. Also, we have designed a hardware and a software filters with smart algorithm for better signal processing of the proposed system. Software approach was adopted to obtain the stable data from A/D converter.

• Journal of Power Electronics
• /
• v.12 no.3
• /
• pp.399-409
• /
• 2012

In DC-DC Buck converters with average current mode control, the current loop compensator provides additional design freedom to enhance the converter current loop performance. On the other hand, the current loop circuit elements append substantial amount of complexity to not only the inner current loop but also the outer voltage loop, which makes it demanding to quantify circuit and operating parameter effects on the small-signal dynamics of such converters. Despite the difficulty, it is shown in this paper that parameter effects can be analyzed satisfactorily by using an existing small-signal model in conjunction with a newly proposed simplified alternative. As a result of the study, new insight into average current mode control is uncovered and discussed quantitatively. Measurable experimental results on a prototype averaged-current-mode-controlled Buck converter are provided to facilitate the analytical study with good correlation.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.62 no.6
• /
• pp.756-761
• /
• 2013

This paper propose the new demodulation method that can detect resolver signal's peak at the time of position estimation when the position information is required during current controller period. The proposed method is performed in a synchronous demodulation way with exciting signal and also cover a capability which can compensate the lag element of exciting signal caused by the resolver's inductive component and filter circuit. This paper carried out the experiment to investigate the validity and performance of the suggested method by using the test board made up of DSP and demodulation circuit. The test results show that the proposed method is theoretically clear and work completely as expected from making sure of sampling resolver signal's peak at the time of position estimation. In addition, Software position tracking algorithm is executed with the demodulated signals generated by the suggested method and an exact position can be estimated.

• Journal of Power Electronics
• /
• v.18 no.2
• /
• pp.482-491
• /
• 2018

The practical design methodology of a three-phase dual active bridge (3ph-DAB) converter applied to low voltage direct current (LVDC) applications is proposed by using a mathematical model based on the steady-state operation. An analysis of the small-signal model (SSM) is important for the design of a proper controller to improve the stability and dynamics of the converter. The proposed lead-lag controller for the 3ph-DAB converter is designed with a simplified SSM analysis including an equivalent series resistor (ESR) for the output capacitor. The proposed controller can compensate the effects of the ESR zero of the output capacitor in the control-to-output voltage transfer function that can cause high-frequency noises. In addition, the performance of the power converter can be improved by using a controller designed by a SSM analysis without additional cost. The accuracy of the simplified SSM including the ESR zero of the output capacitor is verified by simulation software (PSIM). The design methodology of the 3ph-DAB converter and the performance of the proposed controller are verified by experimental results obtained with a 5-kW prototype 3ph-DAB converter.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.2
• /
• pp.113-118
• /
• 2007

In this paper, a novel approach to using Subcircuit of Pspice in designing feedback for DC-DC converter systems is proposed. Proposed new approach, the feedback design procedures which are based on small signal modeling are programmed as a subcircuit in Pspice. For this purpose, Analog Behavioral Modeling (ABM) is used. By using the subcircuit, the component values of the error compensation amplifier can be easily obtained by means of Pspice DC analysis. The methodology of development is presented in detail and application examples demonstrated the effectiveness of the proposed approach in designing feedbacks for DC-DC converters. The converter with PWM method used continuous current mode and calculated buck converter control signal with average and linear current technique. To decide pole and zero K-method was adapted and this kind of design procedure took stable function.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.2
• /
• pp.47-52
• /
• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Journal of Electrical Engineering and Technology
• /
• v.10 no.2
• /
• pp.560-573
• /
• 2015

In this paper, a battery charger is introduced for an interleaved DC-DC converter with an LCLC filter. To improve the overall performance of the DC-DC converter for battery charger, a method is proposed. First, the structure of the system is presented. Second, an LC filter is compared to an LCLC filter in terms of the response characteristics and size. Third, the small-signal model of a bidirectional DC-DC converter using a state-space averaging method and the required transfer functions are introduced. Next, the frequency characteristics of the converter are discussed. Finally, the simulation and experimental results are analyzed to verify the proposed state space of the bidirectional converter.