• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.05a
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• pp.101-102
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• 2006

BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant, It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the sell-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS). respectively. The removal rate of BTO thin film using the $BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%.

• Korean Journal of Optics and Photonics
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• v.16 no.3
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• pp.275-286
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• 2005

The performance of the InGaN LED's in terms of the photon extraction efficiency has been analyzed by the Monte Carlo photon simulation method. Simulation results show that the sidewall slanting scheme, which works well for the AlInGaP or InGaN/SiC LED, plays a very minimal role in InGaN/sapphire LED's. In contrast to InGaN/SiC LED's, the lower refractive index sapphire substrate restricts the generated photons to enter the substrate, minimizing the chances for the photons to be deflected by the slanted sidewalls of the epitaxial semiconductor layers that are usually very thin. The limited photon transmission to the sapphire substrate also degrades the. photon extraction efficiency especially in the epitaxial-side down mount. One approach to exploit the photon extraction potential of the epitaxial-side down mount may be to texture the substrate-epitaxy interface. In this case, randomized photon deflection off the textured interface directly increases the number of the photons entering the sapphire substrate, from which they easily couple out of the chip and thereby improving the photon extraction efficiency drastically.

• Korean Journal of Materials Research
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• v.13 no.4
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• pp.266-270
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• 2003

We studied BCl$_3$ dry etching of GaAs in a planar inductively coupled plasma system. The investigated process parameters were planar ICP source power, chamber pressure, RIE chuck power and gas flow rate. The ICP source power was varied from 0 to 500 W. Chamber pressure, RIE chuck power and gas flow rate were controlled from 5 to 15 mTorr, 0 to 150 W and 10 to 40 sccm, respectively. We found that a process condition at 20 sccm $BCl_3$ 300 W ICP, 100 W RIE and 7.5 mTorr chamber pressure gave an excellent etch result. The etched GaAs feature depicted extremely smooth surface (RMS roughness < 1 nm), vertical sidewall, relatively fast etch rate (> $3000\AA$/min) and good selectivity to a photoresist (> 3 : 1). XPS study indicated a very clean surface of the material after dry etching of GaAs. We also noticed that our planar ICP source was successfully ignited both with and without RIE chuck power, which was generally not the case with a typical cylindrical ICP source, where assistance of RIE chuck power was required for turning on a plasma and maintaining it. It demonstrated that the planar ICP source could be a very versatile tool for advanced dry etching of damage-sensitive compound semiconductors.

• Journal of the Semiconductor & Display Technology
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• v.19 no.1
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• pp.79-84
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• 2020

Unlike a printing process, it is difficult to pattern organic thin films in the longitudinal (coating) direction using a coating process. In this paper, we have investigated the feasibility of patterning organic thin films using needles. To this end, we have slot-coated an aqueous poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) (PEDOT:PSS) solution in the form of a fine stripe or large area and then applied the dual needle; one for discharging the main solvent of the underlying thin film and the other for sucking the dissolved thin film. We have found that the pattern width and depth increase as the moving speed of the plate decreases. However, it is observed that the sidewall slope is very gentle (the length of the slope is of the order of 200 ㎛) due to the fact that the discharged main solvent is widely spread and then isotropic etching occurs. With this scheme, we have also demonstrated that a fine stripe can be obtained by scanning the dual needle closely. To demonstrate its applicability to solution-processable organic light-emitting diodes (OLEDs), we have also fabricated OLED with the patterned PEDOT:PSS stripe and observed the insulation property in the strong light-emitting stripe.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.18 no.12
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• pp.1007-1016
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• 2006

Although the advance in electronic technology enables a large number of circuity to be packed in a small volume, it is simultaneously required to remove the high heat load produced by them. In this study, the heat transfer and pressure drop characteristics of a mini-channel heat exchanger, which is designed for liquid cooling of electronic components, are investigated by varying operating conditions. Water and FC-72 were used as working fluids. The mini-channel heat exchanger was made with circular shape channels having din-meters of 2, 3, and 4 mm in regular intervals, and the channel length was 100 mm. The header and inlet guide pathway to provide uniform inflow were attached at the inlet of the test section. Copper block including the heaters was attached at the sidewall of the test section as a heat source, which provided the heat flux from 5 to $15W/cm^2$. The entrance effects enhanced the heat transfer coefficient in the mini-channel significantly. In addition, the single-phase pressure drop in the mini-channel was very similar to that predicted by the laminar flow correlation except that the transition Re decreased due to flow instability in the entrance region.

• Geophysics and Geophysical Exploration
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• v.2 no.4
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• pp.174-179
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• 1999

Shear wave velocity, one of major elastic constants in the dynamic design for civil structures, is conventionally measured from downhole, crosshole or sonic logging tests. SASW (Spectral Analysis of Surface Waves) method, which overcomes the disadvantage of the in-hole tests, can evaluate subsurface stiffness nondestructively and nonintrusively through measuring surface waves on surface. In this paper, principles of the SASW method are briefly described and the results of various field tests, conducted to investigate the applicability of the method, are summarized. The SASW method was successfully applied in evaluating the effects of dynamic compaction at Inchon international airport site, applied in evaluating the integrity of the lining and sidewall at a testing tunnel located in Mabukri, and applied in detecting thickness of a concrete retaining wall. The results of field tests and the nondestructive and economical characteristics of the method show the promising future of the SASW method in civil engineering projects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• Journal of IKEEE
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• v.18 no.2
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• pp.214-219
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• 2014

In this paper, the usage of tilt-implanted trench Schottky diode(TITSD) based on silicon carbide is proposed. A tilt-implanted trench termination technique modified for SiC is proposed as a method to keep all the potentials confined in the trench insulator when reverse blocking mode is operated. With the side wall doping concentration of $1{\times}10^{19}cm^{-3}$ nitrogen, the termination area of the TITSD is reduced without any sacrifice in breakdown voltage while potential is confined within insulator. When the trench depth is set to 11um and the width is optimized, a breakdown voltage of 2750V is obtained and termination area is 38.7% smaller than that of other devices which use guard rings for the same breakdown voltage. A Sentaurus device simulator is used to analyze the characteristics of the TITSD. The performance of the TITSD is compared to the conventional trench Schottky diode.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.156-161
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• 2006

In this paper, an E-patch antenna on the U-shaped ground plane is designed and experimental studied. In order to reduce to cross-polarization level and to enhance the gain of the microstrip patch antenna, a U-shaped ground plane is employed in the microstrip patch antenna. As a main radiator, an E-shaped patch is used to reduce the antenna size as small as possible. Also to enhance the bandwidth of the antenna, a substrate of the lowest permittivity of which thickness as thick as possible is used and a rectangular patch is overlaid on the air substrate of the E-shaped patch antenna. The radiation characteristics of the antenna are calculated by CST Microwave Studio 5.0 simulation software. Experimental results show that by increasing the height of the sidewall of the ground plane, the antenna gain is increased and the cross-polarization level is decreased.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.