• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2003년도 ICCAS
• /
• pp.970-973
• /
• 2003

Abstract An idea to redce the direct-path short circuit current of the CMOS digital integrated circuit is present. The sample circuit model of the CMOS digital circuit is the CMOS current-control digital output driver circuit, which are also suitable for the low voltage supply integrated circuits as the simple digital inverter, are present in this title. The circuit consists of active MOS load as the current control source, which construct from the saturated n-channel and p-channel MOSFET and the general CMOS inverter circuits. The saturated MOSFET bias can control the output current and the frequency response of the circuit. The experimental results show that lower short circuit current control can make the lower frequency response of the circuit.

• 전자공학회논문지C
• /
• 제35C권1호
• /
• pp.1-9
• /
• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

• 전자공학회논문지SC
• /
• 제39권2호
• /
• pp.140-145
• /
• 2002

본 논문은 단락회로 전류를 없애기 위한 CMOS 버퍼회로에 대한 것이다. 최종 구동소자는 풀-업 PMOS와 풀-다운 NMOS로 구성하고 이를 구동하기 위해 두가지 경로를 입력신호로 선택되도록 하였다. 이러한 기법으로 최종 구동회로가 짧은 시간동안 tri-state가 되어 단락회로 전류를 차단하였다. 모의 실험결과 전원전압 3.3V에서 전력-지연 곱을 기존의 Tapered 버퍼[1]와 비교하여 약 42% 줄일 수 있었다

• Journal of Electrical Engineering and Technology
• /
• 제12권6호
• /
• pp.2278-2288
• /
• 2017

Multilevel converter topologies are widely used in many applications. The cascaded H-bridge multilevel inverter (CHBMI), which is one of many multilevel converter topologies, has been introduced as a useful topology in high and medium power. However, it has a drawback to require a lot of switches. Therefore, the reliability of CHBMI is important factor for analyzing the performance. This paper presents a simple switch fault diagnosis method for single-phase CHBMI. There are two types of switch faults: open-fault and short-fault. In the open-fault, the body diode of faulty switch provides a freewheeling current path. However, when the short-fault occurs, the distortion of output current is different from that of the open-fault because it has an unavailable freewheeling current flow path due to a disconnection of fuse. The fault diagnosis method is based on the zero current time analysis according to zero-voltage switching states. Using the proposed method, it is possible to detect the location of faulty switch accurately. The PSIM simulation and experimental results show the effectiveness of proposed switch fault diagnosis method.

• 한국정보처리학회논문지
• /
• 제3권7호
• /
• pp.1924-1937
• /
• 1996

본 논문에서는 다중 보드를 시험하기 위한 새로운 구조인 확장된 스캔 경로 (ESP: Exlended Scan Path)와 절차를 제안한다. 보드률 시험하기 위한 기존의 구조로는 단일 스캔 경로와 다중 스캔 경로가 있다. 단일 스캔 경로 구조는 시험 데이자의 전송 경로 인 스캔 경로가 하나로 연결되므로 스캔 경로가 단락이나 개방으로 결함이 생기면 나머지 스캔 경로에 올바른 시험 데이타를 입력할 수 없다. 다중 스캔 경로 구조는 다중 보드 시험 시보드마다 별도의 신호선이 추가된다. 그러므로 기존의 주 구조는 다중 보드 시험에는 부적절하다. 제안된 ESP구조를 단일 스캔 경로 구조와 비교하면, 스캔 경로 상에 결함이 발생하더라도 그 결함은 하나의 스캔 경로에만 한정되어 다른 스캔 경로의 시험 데이타에는 영향을 주지 않는다. 뿐만 아니라, 비스트(BIST: BUILT In Self Test)와 IEEE 1149.1 경계면 스캔 시험을 병렬로 수행함으로써 시험에 소요되는 시간을 단축한다. 또한 ESP 구조를 다중 스캔 경로 구조와 비교하면, 스캔 경로마다 신호선을 공통으로 사용함으로써 다중 보드 시험 시 추가되는 신호선이 없다. 본 논문 에서는 제안한 ESP 구조와 기존 시험 구조의 성능을 비교하기 위해서, ISCAS '85벤치 마크 회로를 대상으로 각 구조의 시험 수행 시간을 비교하여 우수함을 보였다.

• Current Optics and Photonics
• /
• 제7권1호
• /
• pp.38-46
• /
• 2023

Optical Fourier-domain reflectometry (OFDR) sensors have been widely used to measure distances with high resolution and speed in a noncontact state. In the electroplating process of a printed circuit board, it is critically important to monitor the copper-plating thickness, as small deviations can lead to defects, such as an open or short circuit. In this paper we employ a phase-based OFDR sensor for in situ relative distance sensing of a sample with nanometer-scale resolution, during electroplating. We also develop an optical-path difference (OPD)-regulated sensing probe that can maintain a preset distance from the sample. This function can markedly facilitate practical measurements in two aspects: Optimal distance setting for high signal-to-noise ratio OFDR sensing, and protection of a fragile probe tip via vertical evasion movement. In a sample with a centimeter-scale structure, a conventional OFDR sensor will probably either bump into the sample or practically out of the detection range of the sensing probe. To address this limitation, a novel OPD-regulated OFDR system is designed by combining the OFDR sensing probe and linear piezo motors with feedback-loop control. By using multiple OFDR sensors, it is possible to effectively monitor copper-plating thickness in situ and uniformize it at various positions.

• 전기전자학회논문지
• /
• 제20권4호
• /
• pp.361-366
• /
• 2016

본 논문에서는 향상된 전기적 특성과 면적효율을 갖는 새로운 구조의 ESD 보호회로를 제안한다. 제안된 회로는 기존의 3-STACK LVTSCR과 비교하여 높은 홀딩전압과 낮은 트리거전압 특성, 향상된 Ron 저항 특성을 갖는다. 제안된 ESD 보호회로는 기존 보호회로 대비 35% 정도의 작은 면적, 35V의 트리거 전압과 8.5V의 홀딩전압을 갖는다. 또한 제안된 ESD 보호회로의 래치-업 면역특성을 향상시키기 위해 기생 바이폴라 트랜지스터들의 유효 베이스 길이를 설계변수로 설정하여 설계하였고 시놉시스사의 TCAD 시뮬레이션을 통하여 제안된 ESD 보호회로를 검증하고 전기적 분석을 실행하였다.

• Bulletin of the Korean Chemical Society
• /
• 제34권9호
• /
• pp.2765-2768
• /
• 2013

The effect of $TiO_2$ nanorods (TNR) and nanoparticles (TNP) composite photoelectrodes and the role of TNR to enhance the energy conversion efficiency in dye-sensitized solar cells (DSSCs) was investigated. The 5% TNR content into the TNP photoelectrode significantly increased the short-circuit current density ($J_{sc}$) and the open-circuit potential ($V_{oc}$) with the overall energy conversion efficiency enhancement of 13.6% compared to the pure TNP photoelectrode. From the photochemical and impedemetric analysis, the increased $J_{sc}$ and $V_{oc}$ for the 5% TNR/TNP composite photoelectrode was attributed to the scattering effect of TNR, reduced electron diffusion path and the suppression of charge recombination between the composite photoelectrode and electrolyte or dye.

• 한국전기전자재료학회논문지
• /
• 제26권4호
• /
• pp.298-303
• /
• 2013

In this study, the W-interconnected dye-sensitized solar cell (DSSC) modules composed of a number of rectangular cells connected in series were investigated, where neighboring cells are processed in reverse. The DSSC modules, a module of dimension about 200 mm ${\times}$ 200 mm, were fabricated with different working electrode width ranging from 5 mm to 21 mm. The short-circuit current of the module increased as the working electrode width increased. Whereas, the decrease in the working electrode width resulted in the increase of the conversion energy efficiency, fill factor, and open-circuit voltage, which is explained by the fact that the possibility that electrons are recombined along their path on the transparent conductive oxide substrate decreases. The module with the conversion energy efficiency of 3.59% was obtained with the working electrode width of 5 mm.

• Journal of electromagnetic engineering and science
• /
• 제7권4호
• /
• pp.147-153
• /
• 2007

This paper represents an analog predistortion linearizer for the high power amplifier with low memory effect. The high power amplifier is implemented using a 90-W peak envelope power(PEP) LDMOSFET at 2.14-GHz and an envelope short matching topology is applied at the active ports to minimize the memory effect. The analog predistortion circuit comprises the fundamental path and the cuber and quintic generating circuits, whose amplitudes and phases can be controlled independently. The predistortion circuit is tested for two-tone and wide-band code division multiple access(WCDMA) 4FA signals. For the WCDMA signal, the adjacent channel leakage ratios(ACLRs) at 5 MHz offset are improved by 12.4 dB at average output powers of 36 dBm and 42 dBm.