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http://dx.doi.org/10.5515/JKIEES.2007.7.4.147

Analog Predistortion High Power Amplifier Using Novel Low Memory Matching Topology  

Kim, Jang-Heon (Department of Electrical Engineering, Pohang University of Science and Technology(POSTECH))
Woo, Young-Yun (Telecommunication R & D Center, Samsung Electronics Company Ltd.)
Cha, Jeong-Hyeon (XRONet Corporation)
Hong, Sung-Chul (Telecommunication R & D Center, Samsung Electronics Company Ltd.)
Kim, Il-Du (Department of Electrical Engineering, Pohang University of Science and Technology(POSTECH))
Moon, Jung-Hwan (Department of Electrical Engineering, Pohang University of Science and Technology(POSTECH))
Kim, Jung-Joon (Department of Electrical Engineering, Pohang University of Science and Technology(POSTECH))
Kim, Bum-Man (Department of Electrical Engineering, Pohang University of Science and Technology(POSTECH))
Publication Information
Journal of electromagnetic engineering and science / v.7, no.4, 2007 , pp. 147-153 More about this Journal
Abstract
This paper represents an analog predistortion linearizer for the high power amplifier with low memory effect. The high power amplifier is implemented using a 90-W peak envelope power(PEP) LDMOSFET at 2.14-GHz and an envelope short matching topology is applied at the active ports to minimize the memory effect. The analog predistortion circuit comprises the fundamental path and the cuber and quintic generating circuits, whose amplitudes and phases can be controlled independently. The predistortion circuit is tested for two-tone and wide-band code division multiple access(WCDMA) 4FA signals. For the WCDMA signal, the adjacent channel leakage ratios(ACLRs) at 5 MHz offset are improved by 12.4 dB at average output powers of 36 dBm and 42 dBm.
Keywords
Ajacent Channel Leakage Ratio(ACLR); Linearization; Memory Effect; Predistortion; Wide-Band Code Division Multiple Access(WCDMA);
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