• 한국통신학회논문지
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• 제12권6호
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• pp.580-598
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• 1987

本 論文은 Galois Field를 利用하여 順序多値論理回路를 實現하는 하나의 방법을 제시하였다. 먼저 Taylor급수를 有限體上에서 成立하는 多項式에 對應하도록 전개시켜 多値組合論理回路의 固有行列을 산출하고 이 行列을 근거로 順序多値論理回路를 設計하였다. 本 論文은 組合回路를 構成하는 基本 개념을 順序論理回路에도 적용될 수 있도록 擴張한 것이다. 本 論文에서는 우선 組合論理回路의 構成理論을 擴張하여 單一入力 單一出力인 경우의 順序多値論理函數構成理論을 提示한 후 이를 擴張하여 單一入力 多出力인 경우의 順序多置論理函數構成理論을 提示하였다. 또한 이를 더욱 擴張하여 單一變數는 물론 多變數 多出力인 경우까지 提示하였다. 이때 多出力인 경우는 回路가 상호 獨立的이므로 Partition 개념에 의하여 처리하였다. 이 방법에 依하여 順序多値論理回路를 設計하면 종래의 多項式전개에 必要한 방대한 계산과정을 줄일 수 있었다. 또한 行列연산에 의하여 계산하므로 아무리 복잡한 論理函數라 하더라도 Computer Program처리가 가능하였다.

• 대한전기학회논문지
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• 제33권4호
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• pp.134-139
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• 1984

This paper presents the computer program to design the synchronous sequential logic circuit. The computer program uses the MASK method to get the circuit of optimal cost. The computer program takes as an input, the minimal reduced state transition table where each state has its internal code. As an output,the optimal design of synchronous sequential logic circuit is generated for each flipflop type of JK,T,D, and RS respectively. And these circuits for 4 flipflop types are evaluated and sorted in ascending order of their costs, so that the user can select the proper flipflop type and its circuit. Furthermore,the proposed computer program may be applied to state assignment with its facility of cost evaluation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.220-223
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• 2002

The digital logic systems(DLS) is classified into digital combinational logic systems(CDLS) and digital sequential logic systems(SDLS). This paper presents a method of constructing the digital sequential logic systems without feedback. Firstly we assign all elements in Finite Fields to P-valued digit codes using mathematical properties of Finine Fields. Also, we discuss the operarional properties of the building block T-gate that is used to realizing digital sequential logic systems over Finite Fields. Then we realize the digital sequential logic systems without feedback. This digital sequential logic systems without feedback is constructed ny following steps. Firstly, we assign the states in the state-transition diagram to state P-valued digit dodo, then we obtain the state function and predecessor table that is explaining the relationship between present state and previous states. Next, we obtained the next-state function and predecessor table. Finally, we realize the circuit using T-gate and decoder.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.168-176
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• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

• 대한전기학회논문지
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• 제32권4호
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• pp.109-120
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• 1983

본 논문은 마이크로프로세서를 이용한 순차 논리회로(Sequential Logic Cricuit)설계에 관한 것이다. 근래에는 많은 순차논리회로가 마이크로프로세서를 이용하여 설계되나, 이 방식은 회로 설계자들에게 익숙하지않은 마이크로프로세서나 그 프로그램에 대한 지식을 필요로 한다. 이 논문에서는 간편하면서도 사용처에 관계없이 잘 적용될 수 있는 표준 프로그램을 제시하였고, 이 프로그램으로 마이크로프로세서나 프로그램에 대하여 잘 모르는 설계자들도 쉽게 설계를 할 수 있을 것이다. 이 프로그램의 적용성과 응용성을 나타내기 위하여 두가지 예를 Z-80 마이크로프로세서로 설계하여 보였다.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권1호
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• 대한전자공학회논문지
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• 제24권5호
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• pp.823-832
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• 1987

This pper presents a method for constructing multiple-valued logic sequential machines based on Galois field. First, we assign all elements in GF(2**m) to bit codes using mathematical properties of GF(2**m). Then, we realized the sequencial machine circuits with and withoutm feed-back. 1) Sequential machines with feed-back are constructed by using only MUX from state-transition diagram expressing the information of sequential machines. 2) Sequential machines without feed-back are constructed by following steps. First, we assigned states in state-transition disgram to state bit codes, then obtained state function and predecessor table explaining the relationship between present states and previous states. Next, we obtained next-state function from state function and predecessor table. Finally we realized the circuit using MUX and decoder.

• 한국정보처리학회논문지
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• 제3권3호
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• pp.564-571
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• 1996

본 논문에서는 새로운 ASIC 구조로 최근에 관심을 모으고 있는 TLU형 FPGA를 위한 순차회로 기술 매핑에 관한 것이다. 본 고에서 제안하는 TLU형 FPGA를 위한 순차회로 기술 매핑방법은 먼저 6개 또는 7개의입력을가지는 조합 및 순차 노드에대해서 전처리 기를 사용하여 한 출력 CLB에매핑하고, 매핑안된나머지 중 순차회로합병 조건에 만족 하는 6개 혹은 7개 입력 변수를 갖는 노드부터 CLB에 매핑한다. 본 고에서 제안한 순차 회로 기술 매핑 방법이 간단하면서 만족스런 수행 시간과 결과를 얻었다. 여러개의 벤치마크 화로를 sis-pga(map_together 및 map_scparate)순차회로 합성 시스템과 비교 하였으며, 실험결과는 본 시스템이 sis-pga 보다 17% 이상 성능이 좋다는 결과를 보여 주고 있다.

• 대한전자공학회논문지
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• 제23권4호
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• pp.460-465
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• 1986

In this paper, a method for constructing of the sequential multiple-valued logic circuits over Galois field GF(px) is proposed. First, we derive the Talyor series over Galois field and the unique matrices which accords with the number of the element over the finite field, and we constdruct sequential multiple-valued logic circuits using these matrices. Computational procedure for traditional polynomial expansion can be reduced by using this method. Also, single and multi-input circuits can be easily implemented.

• 한국시뮬레이션학회논문지
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• 제10권1호
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• pp.25-34
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• 2001

In this paper, we describe the generation method of interface logic which replace between IP & IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new asynchronous sequential "Waveform to VHDL" code creation algorithm by flow chart conversion : Wave2VHDL - if only mixed asynchronous timing waveform is presented the level type input and pulse type input for handshaking, we convert waveform to flowchart and then replace with VHDL code according to converted flowchart. Also, we confirmed that asynchronous electronic circuits are created by applying extracted VHDL source code from suggest algorithm to conventional domestic/abroad CAD Tool, Finally, we assured the simulation result and the suggest timing diagram are identical.