References
- J. F. Ziegler and H. W. Curtis, "IBM experiments in soft fails in computer electronics (1978 - 1994)," IBM Journal of Research and Development, vol. 40, no. 1, pp. 3-18, 1996. https://doi.org/10.1147/rd.401.0003
- D. T. Franco, J.F. Naviner and L. Naviner, "Yield and reliability issues in nanotechnologies," Annales des telecommunications, vol. 61, no. 11-12, pp. 1422-1457, Nov-Dec. 2006. https://doi.org/10.1007/BF03219903
- P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L.Alvisi, "Modeling the effect of technology trends on the soft error rate of combinatorial logic," Proc. Int'l Conf. on Dependable Systems and Networks(DSN), 2002, pp. 389-398.
- H. Asadi and M. B. Tahoori, "Soft error modeling and protection for sequential elements," In Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., Oct. 2005, pp. 463-471.
- K. Mohanram and N. Touba, "Cost-effective approach for reducing soft error failure rate in logic circuits," Test Conference, 2003. Proceedings. ITC 2003. International, vol. 1, pp. 893-901, Sept-Oct, 2003.
- N. S. S. Singh, N. H. Hamid, V. S. Asirvadam, U. Khalid and J. Anwer. "Sensitivity analysis of Probability Transfer Matrix (PTM) on same functionality circuit architectures," In Signal Processing and its Applications (CSPA), 2012 IEEE 8th International Colloquium on, pp. 250-254, 2012.
- S. Mitra, N. Seifert, M. Zhang, Q. Shi and K. Kim, "Robust system design with Built-In soft-error resilience," IEEE Computer, vol. 38, pp. 43-52, Feb. 2005.
- K. Mohammadi, H. Jahanirad and P. Attarsharghi, "Fast reliability analysis method for sequential logic circuits," 21st International Conference on Systems Engineering, 2011, p. 352-356.
- J. Cong and K. Minkovich, "LUT-based FPGA technology mapping for reliability," in Proc. IEEE/ACM Design Autom. Conf., Jun. 2010, pp. 517-522.
- M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. S. Reorda, and A. Paccagnella, "Simulation-based analysis of SEU effects in SRAM-based FPGAs," IEEE Trans. Nucl. Sci., vol. 51, no. 6, p. 3354-3359, Dec. 2007.
- G. Asadi and M. B. Tahoori, "An analytical approach for soft error rate estimation in digital circuits," Proc. IEEE Int'l Symposium on Circuits and Systems, 2005, pp. 2991-2994.
- G. Asadi and M. B. Tahoori, "Soft error rate estimation and mitigation for SRAM-based FPGAs," in Proc. ACM/SIGDA Int. Symp. Field-Program. Gate Arrays, 2005, pp. 149-160.
- H. Asadi and M. B. Tahoori, "Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 15, no. 12, pp. 1320-1331, Dec. 2007. https://doi.org/10.1109/TVLSI.2007.909795
- Keheng Huang, Yu Hu and Xiaowei Li. "Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 22, no. 2, pp. 256-269, 2014. https://doi.org/10.1109/TVLSI.2013.2239318
- Lu Yinghai and Hai Zhou. "Retiming for soft error minimization under error-latching window constraints," In Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1008-1013, 2013.
- Y. Lin and L. He, "Device and architecture concurrent optimization for FPGA transient soft error rate," in Proc. IEEE/ACM Int. Conf. Comput. Aided Design, pp. 194-198, Sep. 2007.