• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.168-176
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• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

• Journal of Multimedia Information System
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• v.6 no.4
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• pp.323-328
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• 2019

In this paper, a method of constructing an advanced sequential circuit over finite fields is proposed. The method proposed an algorithm for assigning all elements of finite fields to digital code from the properties of finite fields, discussed the operating characteristics of T-gate used to construct sequential digital system of finite fields, and based on this, formed sequential circuit without trajectory. For this purpose, the state transition diagram was allocated to the state dependency code and a whole table was drawn showing the relationship between the status function and the current state and the previous state. The following status functions were derived from the status function and the preceding table, and the T-gate and the device were used to construct the sequential circuit. It was confirmed that the proposed method was able to organize sequential digital systems effectively and systematically.

• Journal of Computing Science and Engineering
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• v.6 no.4
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• pp.257-266
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• 2012

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.564-571
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• 1996

The logic synthesis systems for table look up(TLU) type field programmable e gate arrays(FPGAs) have so farstudied mostly the combinational logic problem m. This paper presents for mapping a sequential circuit onto a popular table look up architecture, theXilinx 3090 architecture. In thefirst for solving this problem, combinational and sequential elements which have 6 or7 input combinational and sequential elements which haveless thanor equal to 5 inputs. We heavily use the combinational synthesis techniques tosolve the sequential synthesis problem. Our syntheisis approach is very simple, but its results are reasonable. We compare seveal benchmark Examples with sis-pga(map_together and map_separate) synthesis system and the experimental results show that our synthesis system is 17% betterthan sis-pga sequential synthesis system for TLU PGAs.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.220-223
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• 2002

The digital logic systems(DLS) is classified into digital combinational logic systems(CDLS) and digital sequential logic systems(SDLS). This paper presents a method of constructing the digital sequential logic systems without feedback. Firstly we assign all elements in Finite Fields to P-valued digit codes using mathematical properties of Finine Fields. Also, we discuss the operarional properties of the building block T-gate that is used to realizing digital sequential logic systems over Finite Fields. Then we realize the digital sequential logic systems without feedback. This digital sequential logic systems without feedback is constructed ny following steps. Firstly, we assign the states in the state-transition diagram to state P-valued digit dodo, then we obtain the state function and predecessor table that is explaining the relationship between present state and previous states. Next, we obtained the next-state function and predecessor table. Finally, we realize the circuit using T-gate and decoder.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.823-832
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• 1987

This pper presents a method for constructing multiple-valued logic sequential machines based on Galois field. First, we assign all elements in GF(2**m) to bit codes using mathematical properties of GF(2**m). Then, we realized the sequencial machine circuits with and withoutm feed-back. 1) Sequential machines with feed-back are constructed by using only MUX from state-transition diagram expressing the information of sequential machines. 2) Sequential machines without feed-back are constructed by following steps. First, we assigned states in state-transition disgram to state bit codes, then obtained state function and predecessor table explaining the relationship between present states and previous states. Next, we obtained next-state function from state function and predecessor table. Finally we realized the circuit using MUX and decoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2724-2729
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• 2010

This paper presents a method of constructing the sequential digital systems over finite fields. We assign all elements in finite fields to digit codes using mathematical properties of finite fields. Also, we discuss the operational characteristics and properties of the building block T-gate which is used to implement the sequential digital systems over finite fields. Then, we implemented sequential digital systems without feed-back. The sequential digital systems without feed-back is constructed as following steps. First, we assign the states in state-transition diagram to state digit codes, then obtain the state function and predecessor table which is explaining the relationship between present states and previous states. Next, we obtained the next-state function from state function and predecessor table. Finally we realize the circuit using T-gate and decoder. The proposed method is more efficiency and systematic than previous method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.1-7
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• 2008

Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current drivel circuit.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.5
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• pp.717-722
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• 2016

In this paper, in order to support the peak current limiting function depending on the intensity of the fault current at the early stage of failure, a two magnetically coupled type superconducting fault current limiter (SFCL) is proposed, which includes high-Tc superconducting (HTSC) element 1, where the existing primary and secondary coils are connected to one iron core in parallel, and HTSC element 2, which is connected to the tertiary winding using an additional iron core. The results of the experiments in this study confirmed that the two magnetic coupling type SFCL having coil 1 and coil 2 connected in parallel using dual iron cores is capable of having only HTSC element 1 support the burden of the peak current when a failure occurs. The reason for this is that although HTSC element 1 was quenched and malfunctioned because the instantaneous factor of the initial fault current was large, the current flowing to coil 3 did not exceed the critical current, which would otherwise cause HTSC element 2 to be quenched and not function. In order to limit the peak current upon fault through the sequential HTSC elements, the design should allow it to have the same value as the low value of coil 1 while having coil 3 possess a higher self-inductance value than coil 2. In addition, a short-circuit simulation experiment was conducted to examine and validate the current limiting and recovery characteristics of the SFCL when the winding ratio between coil 1 and coil 2 was 0.25. Through the analysis of the short-circuit tests, the current limiting and recovery characteristics in the case of the additive polarity winding was confirmed to be superior to that of the subtractive polarity winding.