• Title/Summary/Keyword: semiconductor wafer

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Electron Trapping and Transport in Poly(tetraphenyl)silole Siloxane of Quantum Well Structure

  • Choi, Jin-Kyu;Jang, Seung-Hyun;Kim, Ki-Jeong;Sohn, Hong-Lae;Jeong, Hyun-Dam
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.158-158
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    • 2012
  • A new kind of organic-inorganic hybrid polymer, poly(tetraphenyl)silole siloxane (PSS), was invented and synthesized for realization of its unique charge trap properties. The organic portions consisting of (tetraphenyl)silole rings are responsible for electron trapping owing to their low-lying LUMO, while the Si-O-Si inorganic linkages of high HOMO-LUMO gap provide the intrachain energy barrier for controlling electron transport. Such an alternation of the organic and inorganic moieties in a polymer may give an interesting quantum well electronic structure in a molecule. The PSS thin film was fabricated by spin-coating of the PSS solution in THF organic solvent onto Si-wafer substrates and curing. The electron trapping of the PSS thin films was confirmed by the capacitance-voltage (C-V) measurements performed within the metal-insulator-semiconductor (MIS) device structure. And the quantum well electronic structure of the PSS thin film, which was thought to be the origin of the electron trapping, was investigated by a combination of theoretical and experimental methods: density functional theory (DFT) calculations in Gaussian03 package and spectroscopic techniques such as near edge X-ray absorption fine structure spectroscopy (NEXAFS) and photoemission spectroscopy (PES). The electron trapping properties of the PSS thin film of quantum well structure are closely related to intra- and inter-polymer chain electron transports. Among them, the intra-chain electron transport was theoretically studied using the Atomistix Toolkit (ATK) software based on the non-equilibrium Green's function (NEGF) method in conjunction with the DFT.

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Electrodeposition for the Fabrication of Copper Interconnection in Semiconductor Devices (반도체 소자용 구리 배선 형성을 위한 전해 도금)

  • Kim, Myung Jun;Kim, Jae Jeong
    • Korean Chemical Engineering Research
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    • v.52 no.1
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    • pp.26-39
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    • 2014
  • Cu interconnection in electronic devices is fabricated via damascene process including Cu electrodeposition. In this review, Cu electrodeposition and superfilling for fabricating Cu interconnection are introduced. Superfilling results from the influences of organic additives in the electrolyte for Cu electrodeposition, and this is enabled by the local enhancement of Cu electrodeposition at the bottom of filling feature formed on the wafer through manipulating the surface coverage of organic additives. The dimension of metal interconnection has been constantly reduced to increase the integrity of electronic devices, and the width of interconnection reaches the range of few tens of nanometer. This size reduction raises the issues, which are the deterioration of electrical property and the reliability of Cu interconnection, and the difficulty of Cu superfilling. The various researches on the development of organic additives for the modification of Cu microstructure, the application of pulse and pulse-reverse electrodeposition, Cu-based alloy superfilling for improvement of reliability, and the enhancement of superfilling phenomenon to overcome the current problems are addressed in this review.

Properties of Silicon Nitride Deposited by RF-PECVD for C-Si solar cell (결정질 실리콘 태양전지를 위한 실리콘 질화막의 특성)

  • Park, Je-Jun;Kim, Jin-Kuk;Song, Hee-Eun;Kang, Min-Gu;Kang, Gi-Hwan;Lee, Hi-Deok
    • Journal of the Korean Solar Energy Society
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    • v.33 no.2
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    • pp.11-17
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    • 2013
  • Silicon nitride($SiN_x:H$) deposited by radio frequency plasma enhanced chemical vapor deposition(RF-PECVD) is commonly used for anti-reflection coating and passivation in crystalline silicon solar cell fabrication. In this paper, characteristics of the deposited silicon nitride was studied with change of working pressure, deposition temperature, gas ratio of $NH_3$ and $SiH_4$, and RF power during deposition. The deposition rate, refractive index and effective lifetime were analyzed. The (100) p-type silicon wafers with one-side polished, $660-690{\mu}m$, and resistivity $1-10{\Omega}{\cdot}cm$ were used. As a result, when the working pressure increased, the deposition rate of SiNx was increased while the effective life time for the $SiN_x$-deposited wafer was decreased. The result regarding deposition temperature, gas ratio and RF power changes would be explained in detail below. In this paper, the optimized condition in silicon nitride deposition for silicon solar cell was obtained as 1.0 Torr for the working pressure, $400^{\circ}C$ for deposition temperature, 500 W for RF power and 0.88 for $NH_3/SiH_4$ gas ratio. The silicon nitride layer deposited in this condition showed the effective life time of > $1400{\mu}s$ and the surface recombination rate of 25 cm/s. The crystalline silicon solar cell fabricated with this SiNx coating showed 18.1% conversion efficiency.

Efficient Stripping of High-dose Ion-implanted Photoresist in Supercritical Carbon Dioxide (초임계 이산화탄소를 이용한 고농도이온주입 포토레지스트의 효율적인 제거)

  • Kim, Do-Hoon;Lim, Eu-Sang;Lim, Kwon-Taek
    • Clean Technology
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    • v.17 no.4
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    • pp.300-305
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    • 2011
  • A mixture of supercritical carbon dioxide and a co-solvent was employed to strip a high-dose ion-implanted photoresist (HDIPR) from the surface of semiconductor wafers. The stripping efficiency was highly improved by the physical force generated from a ultrasonication tip inside the reactor. In addition, helium gas was injected in the reactor as a barrier gas before the introduction of pure supercritical $CO_2$ ($scCO_2$), which reduced the rinsing time significantly. The effect of co-solvents on the stripping efficiency was investigated. The wafer surfaces were analyzed by scanning electron microscopy and by an energy dispersive X-ray spectrometer.

Growth characteristics of single-crystalline 6H-SiC homoepitaxial layers grown by a thermal CVD (화학기상증착법으로 성장시킨 단결정 6H-SiC 동종박막의 성장 특성)

  • 장성주;설운학
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.10 no.1
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    • pp.5-12
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    • 2000
  • As a semiconductor material for electronic devices operated under extreme environmental conditions, silicon carbides (SiCs) have been intensively studied because of their excellent electrical, thermal and other physical properties. The growth characteristics of single- crystalline 6H-SiC homoepitaxial layers grown by a thermal chemical vapor deposition (CVD) were investigated. Especially, the successful growth condition of 6H-SiC homoepitaxial layers using a SiC-uncoated graphite susceptor that utilized Mo-plates was obtained. The CVD growth was performed in an RF-induction heated atmospheric pressure chamber and carried out using off-oriented ($3.5^{\circ}$tilt) substrates from the (0001) basal plane in the <110> direction with the Si-face side of the wafer. In order to investigate the crystallinity of grown epilayers, Nomarski optical microscopy, transmittance spectra, Raman spectroscopy, XRD, Photoluninescence (PL) and transmission electron microscopy (TEM) were utilized. The best quality of 6H-SiC homoepitaxial layers was observed in conditions of growth temperature $1500^{\circ}C$ and C/Si flow ratio 2.0 of $C_3H_8$ 0.2 sccm & $SiH_4$ 0.3 sccm.

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Fabrication of Bump-type Probe Card Using Bulk Micromachining (벌크 마이크로머시닝을 이용한 Bump형 Probe Card의 제조)

  • 박창현;최원익;김용대;심준환;이종현
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.3
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    • pp.661-669
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    • 1999
  • A probe card is one of the most important pan of test systems as testing IC(integrated circuit) chips. This work was related to bump-type silicon vertical probe card which enabled simultaneous tests for multiple semiconductor chips. The probe consists of silicon cantilever with bump tip. In order to obtain optimum size of the cantilever, the dimensions were determined by FEM(finite element method) analysis. The probe was fabricated by RIE(reactive ion etching), isotropic etching, and bulk-micromachining using SDB(silicon direct bonding) wafer. The optimum height of the bump of the probe detemimed by FEM simulation was 30um. The optimum thickness, width, and length of the cantilever were 20 $\mum$, 100 $\mum$,and 400 $\mum$,respectively. Contact resistance of the fabricated probe card measured at contact resistance testing was less than $2\Omega$. It was also confirmed that its life time was more than 20,000 contacts because there was no change of contact resistance after 20,000 contacts.

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Fabrication and Characterization of Array Type of Single Photon Counting Digital X-ray Detector (Array Type의 Single Photon Counting Digital X-ray Detector의 제작 및 특성 평가)

  • Seo, Jung-Ho;Lim, Hyun-Woo;Park, Jin-Goo;Huh, Young;Jeon, Sung-Chea;Kim, Bong-Hui
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.32-32
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    • 2008
  • X-ray detector는 의료용, 산업용 등 다양한 분야에서 사용되어지고 있으며 기존의 Analog X-ray 방식의 환경오염, 저장공간 부족, 실시간 분석의 어려움 등의 문제점들을 해결하기 위하여 Digital X-ray로의 전환과 연구가 활발하며 이에 따른 관심도 높아지고 있는 살점이다. Digital X-ray detector는 p-영역과 n-영역 사이에 아무런 불순물을 도핑하지 않은 진성반도체(intrinsic semiconductor) 층을 접합시킨 이종접합 PIN 구조의 photodiode 이다. 이 소자는 역바이어스를 가해주면 p영역과 n영역 사이에서 캐리어 (carrier)가 존재하지 않는 공핍 영역이 발생하게 된다. 이런 공핍 영역에서 광흡수가 일어나면, 전자-정공 쌍이 발생한다. 그리고, 발생한 전자-정공 쌍에 전압이 역방향으로 인가되는 경우, 전자는 양의 전극으로 이동하고, 정공은 음의 전극으로 이동한다. 이와 같이, 발생한 캐리어들을 검출하여 전기적인 신호로 변환 시킨다. 고해상도의 Digital X-ray detector를 만들기 위해서는 누설전류에 의한 noise 감소와 소자의 높은 안정성과 내구성을 위한 높은 breakdown voltage를 가져야 한다. 본 연구에서는 Digital X-ray detector의 leakage current 감소와 breakdown voltage를 높이기 위하여 guradring과 gettering technology를 사용하여 전기적 특성을 분석하였다. 기판으로는 $10k\Omega{\cdot}cm$ resistivity를 갖으며, n-type <111>인 1mm 두께의 4인치 Si wafer를 사용하였다. 그리고 pixel pitch는 $100{\mu}m$이며 active area는 $80{\mu}m{\times}80{\mu}m$$32\times32$ array를 형성하여 X-ray를 조사하여 소자의 특성을 평가 하였다.

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A Study on Slurry Isolation Through Chemical Processing, with Comparative Analysis and Validation (화학적 처리를 적용한 Slurry 분리 및 비교분석 검증 연구)

  • Na, Wonshik
    • Journal of Digital Contents Society
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    • v.14 no.1
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    • pp.35-40
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    • 2013
  • The use of slurry with a mix of abrasives and coolant for making Wire Saw in the photovoltaic industry has sharply increased with the semiconductor wafer. In this paper, the slurry was isolated, purified and dried by microwave drying method with high-purity silicon carbide powder obtained through chemical processing. Dried slurry bulk was first pulverized and chemical treatment was applied to produce powder. The produced slurry powder was then analyzed by going through the following analysis; thermal analysis, particle size analyses: SEM shots, elemental analysis, XRF and XRD. The results of this study found the recovery rate of the power obtained though the chemical processing to be higher than the one obtained from mineral processing. The results anticipate infrastructure building and active responses to increasingly stronger domestic and international environmental regulations through the integration and recycling of large amounts of slurry in the photovoltaic industry.

Characteristics of Sapphire Wafers Polishing Depending on Ion Conductivity of Silica Sol (실리카졸의 이온전도도 변화에 따른 사파이어 웨이퍼의 연마 특성)

  • Na, Ho Seong;Cho, Gyeong Sook;Lee, Dong-Hyun;Park, Min-Gyeong;Kim, Dae Sung;Lee, Seung-Ho
    • Korean Journal of Materials Research
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    • v.25 no.1
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    • pp.21-26
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    • 2015
  • CMP(Chemical Mechanical Polishing) Processes have been used to improve the planarization of the wafers in the semiconductor manufacturing industry. Polishing performance of CMP Process is determined by the chemical reaction of the liquid sol containing abrasive, pressure of the head portion and rotational speed of the polishing pad. However, frictional heat generated during the CMP process causes agglomeration of the particles and the liquidity degradation, resulting in a non-uniform of surface roughness and surface scratch. To overcome this chronic problem, herein, we introduced NaCl salt as an additive into silica sol for elimination the generation of frictional heat. The added NaCl reduced the zata potential of silica sol and increased the contact surface of silica particles onto the sapphire wafer, resulting in increase of the removal rate up to 17 %. Additionally, it seems that the silica particles adsorbed on the polishing pad decreased the contact area between the sapphire water and polishing pad, which suppressed the generation of frictional heat.

Endpoint Detection Using Hybrid Algorithm of PLS and SVM (PLS와 SVM복합 알고리즘을 이용한 식각 종료점 검출)

  • Lee, Yun-Keun;Han, Yi-Seul;Hong, Sang-Jeen;Han, Seung-Soo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.9
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    • pp.701-709
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    • 2011
  • In semiconductor wafer fabrication, etching is one of the most critical processes, by which a material layer is selectively removed. Because of difficulty to correct a mistake caused by over etching, it is critical that etch should be performed correctly. This paper proposes a new approach for etch endpoint detection of small open area wafers. The traditional endpoint detection technique uses a few manually selected wavelengths, which are adequate for large open areas. As the integrated circuit devices continue to shrink in geometry and increase in device density, detecting the endpoint for small open areas presents a serious challenge to process engineers. In this work, a high-resolution optical emission spectroscopy (OES) sensor is used to provide the necessary sensitivity for detecting subtle endpoint signal. Partial Least Squares (PLS) method is used to analyze the OES data which reduces dimension of the data and increases gap between classes. Support Vector Machine (SVM) is employed to detect endpoint using the data after PLS. SVM classifies normal etching state and after endpoint state. Two data sets from OES are used in training PLS and SVM. The other data sets are used to test the performance of the model. The results show that the trained PLS and SVM hybrid algorithm model detects endpoint accurately.