• Title/Summary/Keyword: semiconductor simulation

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Simulation of Vacuum Characteristics in Semiconductor Processing Vacuum System by the Combination of Vacuum Pumps (진공펌프 조합에 의한 반도체공정 진공시스템 진공특성 전산모사)

  • Kim, Hyung-Taek;Kim, Dae-Yeon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.6
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    • pp.449-457
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    • 2011
  • Effect of pump combinations on the vacuum characteristics of vacuum system was simulated for optimum design of system. In this investigation, the feasibility of modelling mechanism for VacSimMulti simulator was proposed. Simulation results of various pumping combinations showed the possibilities and reliabilities of simulation for the performance of vacuum system in specific semiconductor processing. Simulation of roughing pump presented the expected pumping behaviors based on commercial specifications of employed pumps. Application of booster pump exhibited the high pumping efficiency for middle vacuum range. Combinations of optimum backing pump for diffusion and turbo vacuum system were obtained. And, the predictable characteristics of process application of both simulated systems were also acquired.

Simulation of Piezoelectric Dome-Shaped-Diaphragm Acoustic Transducers

  • Han, Cheol-Hyun;Kim, Eun-Sok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.1
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    • pp.17-23
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    • 2005
  • This paper describes the simulation of a micromachined dome-shaped-diaphragm acoustic transducer built on a $1.5{\mu}m$ thick silicon nitride diaphragm ($2,000{\mu}m$ in radius, with a circular clamped boundary on a silicon substrate) with electrodes and piezoelectric ZnO film in a silicon substrate. Finite element analysis with ANSYS 5.6 has been performed to analyze the static and dynamic behaviors of the transducer under both pressure and voltage loadings.

A Study of Wire Sweep During Encapsulation of Semiconductor Chips

  • Han, Se-Jin;Huh, Yong-Jeong
    • Journal of the Microelectronics and Packaging Society
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    • v.7 no.4
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    • pp.17-22
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    • 2000
  • In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.

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Scheduling Simulator for Semiconductor Fabrication Line (반도체 FAB의 스케줄링 시뮬레이터 개발)

  • Lee, Young-Hoon;Cho, Han-Min;Park, Jong-Kwan;Lee, Byung-Ki
    • IE interfaces
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    • v.12 no.3
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    • pp.437-447
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    • 1999
  • Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

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Study on Evaporating Process Modeling for Estimation of Thin-film Thickness Distribution (박막두께 예측을 위한 증착 공정 모델링에 관한 연구)

  • Lee Eung-Ki;Lee Dong-Eun;Lee Sook-Han
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2006.05a
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    • pp.156-159
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    • 2006
  • In order to design an evaporation system, geometric simulation of film thickness distribution profile is required. In this paper, a geometric modeling algorithm is introduced for process simulation of the evaporating process. The physical fact of the evaporating process is modeled mathematically. Based on the developed method, the thickness of the thin-film layer can be successfully controlled.

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Evaporation Process Modeling for Large OLED Mass-fabrication System (대면적 유기EL 양산 장비 개발을 위한 증착 공정 모델링)

  • Lee, Eung-Ki
    • Journal of the Semiconductor & Display Technology
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    • v.5 no.4 s.17
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    • pp.29-34
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    • 2006
  • In order to design an OLED(Organic Luminescent Emitting Device) evaporation system, geometric simulation of film thickness distribution profile is required. For the OLED evaporation process, thin film thickness uniformity is of great practical importance. In this paper, a geometric modeling algorithm is introduced for process simulation of the OLED evaporating process. The physical fact of the evaporating process is modeled mathematically. Based on the developed method, the thickness of the thin-film layer can be successfully controlled.

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All-optical Regenerator Using Semi-reflective Semiconductor Optical Amplifier

  • Kim T.Y.;Kim J.Y.;Han S.K.
    • Journal of the Optical Society of Korea
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    • v.10 no.1
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    • pp.11-15
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    • 2006
  • We have proposed and theoretically verified an optical regenerator using a single semi-reflective semiconductor optical amplifier (SR-SOA). To explain the operation characteristics and the operation condition of the proposed opticalregenerator, the simplified gain model for the SR-SOA is introduced and confirmed by comparing the result of the SOA simulation based on the transfer matrix method (TMM). The simulation results show that both extinction ratio (ER) enhancement and signal amplification can be achieved in the proposed regenerator.

Thermal Diffusion Process Modeling with Adaptive Finite Volume Method (적응성 유한체적법을 적용한 다차원 확산공정 모델링)

  • 이준하;이흥주
    • Journal of the Semiconductor & Display Technology
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    • v.3 no.3
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    • pp.19-21
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    • 2004
  • This paper presents a 3-dimensional diffusion simulation with adaptive solution strategy. The developed diffusion simulator VLSIDIF-3 was designed to re-refine areas. Refine scheme was calculated by the difference of doping concentration between any of two nodes. Each element is greater than tolerance and redo diffusion process until error is tolerable. Numerical experiment in low doping diffusion problem showed that this adaptive solution strategy is very efficient in both memory and time, and expected this scheme would be more powerful in complex diffusion model.

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Automatic classify of failure patterns in semiconductor fabrication for yield improvement (수율 향상을 위한 반도체 공정에서의 불량 유형 자동 분류)

  • 한영신;최성윤;김상진;황미영;이칠기
    • Proceedings of the Korea Society for Simulation Conference
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    • 2003.11a
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    • pp.147-151
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    • 2003
  • Yield enhancement in semiconductor fabrication is important. Even though DRAM yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form patterns, it is usually an indication for the identification of equipment problems or process variations. In this paper describes the techniques to automatically classify a failure pattern using a fail bit map.

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Breakdown characteristics of the SOI LIGBT with dual-epi layer (이중 에피층을 가지는 SOI LIGBT의 에피층 두께에 따른 항복전압 특성 분석)

  • Kim, Hyoung-Woo;Kim, Sang-Cheol;Seo, Kil-Soo;Bahng, Wook;Kim, Nam-Kyun;Kim, Eun-Dong
    • Proceedings of the KIEE Conference
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    • 2004.07c
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    • pp.1585-1587
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    • 2004
  • 이중 에피층 구조를 가지는 SOI(Silicon-On-Insulator) LIGBT(Lateral Insulated Gate Bipolar Transistor)의 에피층 두께 변화에 따른 항복전압 특성을 분석하였다. 제안된 소자는 전하보상효과를 얻기 위해 n/p-epi의 이중 에피층 구조를 사용하였으며, 에피층 전체에 걸쳐서 전류가 흐를 수 있도록 하기 위해 trenched anode구조를 채택하였다. 본 논문에서는 n/p-epi층의 농도를 고정시킨 후 각각의 epi층의 두께를 변화시켜가며 simulation을 수행하였을 때 항복전압의 변화 및 표면과 epi층에서의 전계분포변화를 분석하였다.

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