• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.1-5
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• 2016

In order to apply sub-resolution assist feature (SRAF) in extreme ultraviolet lithography, the maximum non-printing SRAF width and lithography process margin needs to be improved. Through simulation, we confirmed that the maximum SRAF width of 6% attenuated phase shift mask (PSM) is large compared to conventional binary intensity mask. The increase in SRAF width is due to dark region's reflectivity of PSM which consequently improves the process window. Furthermore, the critical dimension error caused by variation of SRAF width and center position is reduced by lower change in diffraction amplitude. Therefore, we speculate that the margin of SRAF application will be improved by using PSM.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.731-736
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• 2001

Nowadays various simulation tools are widely used for the design and the analysis of power electronic converters. From the engineering point of view it is rather difficult to parameterize power semiconductor device models without the knowledge of basic physical parameters. In recent years some data sheet driven behavioral models or so called 'wizard' tools have been introduced to solve this problem. In this contribution some experiences with some user-friendly power semiconductor models will be discussed. Using special simulation test circuits it is possible to get information on the static and dynamic behavior of the parameterized models before they are applied in more complex schemes. These results can be compared with data sheets or with measurements. The application of these models for power loss analysis of inverter type arc welding power sources will be described.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.65-70
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• 2013

A 0.18-${\mu}m$ 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.45-48
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• 2002

This paper discusses the surface roughness of negative chemically amplified resists, SAL601 exposed by I-beam direct writing. system. Surface roughness, as measured by atomic force microscopy, have been simulated and compared to experimental results. Molecular-scale simulator predicts the roughness dependence on material properties and process conditions. A chemical amplification is made to occur in the resists during PEB process. Monte-Carlo and exposure simulations are used as the same program as before. However, molecular-scale PEB simulation has been remodeled using a two-dimensional molecular lattice representation of the polymer matrix. Changes in surface roughness are shown to correlate with the dose of exposure and tile baking time of PEB process. The result of simulation has a similar tendency with that of experiment.

• IE interfaces
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• v.25 no.2
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• pp.264-275
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• 2012

The process of semiconductor(IC Package) manufacturing usually includes lots of complex and sequential processes. Many kinds of equipments are installed with the mixed concept of serial and parallel manufacturing system. The business environments of the semiconductor industry have been changed frequently, because new technologies are developed continuously. It is the main reason of new investment plan and layout consideration. However, it is difficult to change the layout after installation, because the major equipments are expensive and difficult to move. Furthermore, it is usually a multiple-objective problem. Thus, new investment or layout change should be carefully considered when the production environments likewise product mix and production quantity are changed. This paper introduces a simulation case study of a Korean company that produces packaging substrates(especially lead frames) and requires multi-objective decision support. $QUEST^{(R)}$ is used for simulation modelling and AHP(Analytic Hierarchy Process) and DEA(Data Envelopment Analysis) are used for weighting of qualitative performance measures and solving multiple-objective layout problem, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.797-801
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• 2014

This research presented the concept of employing the punch-through diode triggered SCRs (PTTSCR) for low voltage ESD applications such as transient voltage suppression (TVS) devices. In order to demonstrate the better electrical properties, various traditional ESD protection devices, including a silicon controlled rectifier (SCR) and Zener diode, were simulated and analyzed by using the TCAD simulation software. The simulation result demonstrates that the novel PTTSCR device has better performance in responding to ESD properties, including DC dynamic resistance and capacitance, compared to SCR and Zener diode. Furthermore, the proposed PTTSCR device has a low reverse leakage current that is below $10^{-12}$ A, a low capacitance of $0.07fF/mm^2$, and low triggering voltage of 8.5 V at $5.6{\times}10^{-5}$ A. The typical properties couple with the holding voltage of 4.8 V, while the novel PTTSCR device is compatible for protecting the low voltage, high speed ESD protection applications. It proves to be good candidates as ultra-low capacitance TVS devices.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.107-113
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• 2024

Scheduling of semiconductor test facilities has been crucial since effective scheduling contributes to the profits of semiconductor enterprises and enhances the quality of semiconductor products. This study aims to solve the scheduling problems for the wafer burn-in test facilities of the semiconductor back-end process by utilizing simulation and deep reinforcement learning-based methods. To solve the scheduling problem considered in this study. we propose novel state, action, and reward designs based on the Markov decision process. Furthermore, a neural network is trained by employing the recent RL-based method, named proximal policy optimization. Experimental results showed that the proposed method outperformed traditional heuristic-based scheduling techniques, achieving a higher due date compliance rate of jobs in terms of total job completion time.

• Journal of the Semiconductor & Display Technology
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• v.6 no.2 s.19
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• pp.49-52
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• 2007

Characteristics of an active pixel switch readout circuit were studied by SPICE simulation. A simple readout circuit consists of an operation amplifier, a diode, and a down-counter was suggested, and its successful operation was verified by showing that the differences in the detected signal intensity are accordingly converted to modulation of the voltage pulses generated by the comparator. A scheme to use these pulses to generate the original image was also put forward.

• Journal of the Semiconductor & Display Technology
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• v.3 no.3
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• pp.27-29
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• 2004

The responses of hypothetical silicon nanotubes under torsion have been investigated using an atomistic simulation based on the Tersoff potential. A torque, proportional to the deformation within Hooke's law, resulted in the ribbon-like flattened shapes and eventually led to a breaking of hypothetical silicon nanotubes. Each shape change of hypothetical silicon nanotubes corresponded to an abrupt energy change and a singularity in the strain energy curve as a function of the external tangential force, torque, or twisted angle. The dynamics of silicon nanotubes under torsion can be modelled in the continuum elasticity theory.

• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.