• Clean Technology
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• v.5 no.1
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• pp.62-77
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• 1999

Semiconductor industry has rapidly grown because of the need from electronic and computer industries. However the global environmental regulations for various hazardous chemical compounds, which are indispensably used in semiconductor manufacturing process, are getting stronger. The semiconductor industries should develop the cleaner technologies in order to both lead the future world market and avoid the regulations form environmentally developed countries. In this paper, cleaner technologies for semiconductor cleaning processes are surveyed, such as gas phase process, UV process, and plasma process. Advantages and disadvantages of these processes are discussed.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.101-105
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• 2011

In case of high-tech process industries such as semiconductor and TFT-LCD manufactures, fault of a virtually finished product that is value-added one, since it has gone throughout the most of processes, may give rise to quality cost nearly amount to its selling price and can be a main cause that decreases the efficiency of manufacturing process. This paper proposes a real-time dispatching algorithm for semiconductor manufacturing process with rework. In order to evaluate the proposed algorithm, this paper examines the performance of the proposed method by comparing it with that of the existing dispatching algorithms, based on various experimental data.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.16-21
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• 2020

How accurately reproducible energy is delivered to the wafer in the process of making thin films using PE-CVD (Plasma enhanced chemical vapor deposition) during the semiconductor process. This is the most important technique, and most of the reaction on the wafer surface is made by thermal energy. In this study, we studied the method of monitoring the change of thermal energy transferred to the wafer surface by monitoring the temperature change according to the change of the thin film formed on the showerhead facing the wafer. Through this research, we could confirm the monitoring of wafer thin-film which is changed due to abnormal operation and accumulation of equipment, and we can expect improvement of semiconductor quality and yield through process reproducibility and equipment status by real-time monitoring of problem of deposition process equipment performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1220-1224
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• 2007

The effects of plasma damages to the organic thin film transistor (OTFT) during the fabrication process are investigated; metal deposition process on the organic gate insulator by plasma sputtering mainly generates the process induced damages of bottom contact structured OTFTs. For this study, various deposition methods (thermal evaporation, plasma sputtering, and neutral beam based sputtering) and metals (gold and Indium-Tin Oxide) have been tested for their damage effects onto the Poly 4-vinylphenol(PVP) layer surface as an organic gate insulator. The surface damages are estimated by measuring surface energies and grain shapes of organic semiconductor on the gate insulator. Unlike thermal evaporation and neutral beam based sputtering, conventional plasma sputtering process induces serious damages onto the organic surface as increasing surface energy, decreasing grain sizes, and degrading TFT performance.

• Journal of Information Display
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• v.5 no.1
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• pp.28-33
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• 2004

A high voltage NMOSFET is proposed to drive top emission organic light emitting device (OLED) used in the organic electroluminescent (EL) display on the single crystal silicon substrate. The high voltage NMOSFET can be fabricated by utilizing a simple layout technique with a standard CMOS logic process. It is clearly shown that the maximum supply voltage ($V_{DD}$) required for the pixel-driving transistor could reach 45 V through analytic and experimental methods. The high voltage NMOSFET was fabricated by using a standard 1.5 ${\mu}m$, 5 V CMOS logic process. From the measurements, we confirmed that the high voltage NMOSFET could sustain the excellent saturation characteristic up to 50 V without breakdown phenomena.

• IE interfaces
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• v.20 no.3
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• pp.277-287
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• 2007

Semiconductor manufacturing is one of the most complex and capital-intensive processes composed of several hundreds of operations. In today’s competitive business environments, it is more important than ever before to manage manufacturing process effectively to achieve better performances in terms of customer satisfaction and productivity than those of competitors. So, many semiconductor manufacturing companies implement advanced planning and scheduling (APS) system as a management tool for the complex semiconductor manufacturing process. In this study, we explain roles of production planning and scheduling in semiconductor manufacturing and principal factors that make the production planning and scheduling more difficult. We describe the APS system implementation project at Korean semiconductor manufacturing company in terms of key issues with realistic samples.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.53-58
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• 2023

The storage capacity of 3D-NAND flash memory has been enhanced by the multi-layer dielectrics. The deposition process has become more challenging due to the tight process margin and the demand for accurate process control. To reduce product costs and ensure successful processes, process diagnosis techniques incorporating artificial intelligence (AI) have been adopted in semiconductor manufacturing. Recently there is a growing interest in process diagnosis, and numerous studies have been conducted in this field. For higher model accuracy, various process and sensor data are required, such as optical emission spectroscopy (OES), quadrupole mass spectrometer (QMS), and equipment control state. Among them, OES is usually used for plasma diagnostic. However, OES data can be distorted by viewport contamination, leading to misunderstandings in plasma diagnosis. This issue is particularly emphasized in multi-dielectric deposition processes, such as oxide and nitride (ON) stack. Thus, it is crucial to understand the potential misunderstandings related to OES data distortion due to viewport contamination. This paper explores the potential for misunderstanding OES data due to data distortion in the ON stack process. It suggests the possibility of excessively evaluating process drift through comparisons with a QMS. This understanding can be utilized to develop diagnostic models and identify the effects of viewport contamination in ON stack processes.

• International Journal of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.20-26
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• 2017

Process control is crucial in many industries, especially in semiconductor manufacturing. In such large-volume multistage manufacturing systems, a product has to go through a very large number of processing steps with reentrant) before being completed. This manufacturing system has many machines of different types for processing a high mix of products. Each process step has specific quality standards and most of them have nonlinear dynamics due to physical and/or chemical reactions. Moreover, many of the processing steps suffer from drift or disturbance. To assure high stability and yield, on-line quality monitoring of the wafers is required. In this paper we develop a real-time fault detection system on semiconductor manufacturing process. Proposed system is superior to other incremental fault detection system and shows similar performance compared to batch way.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.108-112
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• 2023

Precision manufacturing technology is rapidly developing due to the extreme miniaturization of semiconductor processes to comply with Moore's Law. Accurate and precise alignment, which is one of the key elements of the semiconductor pre-process and post-process, is very important in the semiconductor process. The center detection of wafer align marks plays a key role in improving yield by reducing defects and research on accurate detection methods for this is necessary. Methods for accurate alignment using traditional image sensors can cause problems due to changes in image brightness and noise. To solve this problem, engineers must go directly into the line and perform maintenance work. This paper emphasizes that the development of AI technology can provide innovative solutions in the semiconductor process as high-resolution image and image processing technology also develops. This study proposes a new wafer center detection method through variable thresholding. And this study introduces a method for detecting the center that is less sensitive to the brightness of LEDs by utilizing a high-performance object detection model such as YOLOv8 without relying on existing algorithms. Through this, we aim to enable precise wafer focus detection using artificial intelligence.