• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.136-139
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• 2004

The requirement of planarity, such as with-in-wafer nonuniformity, post thickness range, have become increasingly stringent as critical dimensions of devices are decreased and a better control of a planarity become important. The key factors influencing the planarity capability of the CMP process have been well understood through numerous related experiments. These usually include parameters such as process pressures, relative velocities, slurry temperature, polishing pad materials and polishing head structure. Many study have been done about polishing pad and its groove structure because it's considered as one of the key factors which can decide wafer uniformity directly. But, not many study have been done about polisher head structure, especially about polisher head plate design. The purpose of this paper is to know how the plate structure can affect wafer uniformity and how to deteriorate wafer yield. Furthermore, we studied several new designed plate to improve wafer uniformity and also improve wafer yield.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.504-508
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• 2022

Single crystal gallium oxide (Ga₂O₃) has been an emerging material for power semiconductor applications. However, the defect distribution of Ga₂O₃ substrates needs to be carefully characterized to improve crystal quality during crystal growth. We analyzed the type and the distribution of defects on commercial (-201) Ga₂O₃ substrates to get a basic standard prior to growing Ga₂O₃ crystals. Etch pit technique was employed to expose the type of defects on the Ga₂O₃ substrates. Synchrotron white beam X-ray topography was also utilized to observe the defect distribution by a nondestructive manner. We expect that the observation of defect distribution with three-dimensional geometry will also be useful for other crystal planes of Ga₂O₃ single crystals.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.278-283
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• 2013

This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{\mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{\mu}W$ and chip area is $75{\mu}m{\times}90{\mu}m$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.1096-1099
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• 2001

The basic design structure of RC-GCTs (Reserve-Conducting Gate-Commutated Thyristors) is firstly given in this paper. The bulk of wafer is punch-through (PT) type with high resistivity and narrow N-base width. The photo-mask was designed upon the turn-off characteristics of GCT and solution of separation between GCT and diode part. The center part of Si wafer is free-wheeling diode (FWD) and outer is GCT part which has 240 fingers totally. The switching performance of GCT was investigated by Dessis of ISE. The basic manufacture process of 2500V-4500V RC-GCTs was given in this work. Additionally, the local carrier lifetime control by 5Mev proton irradiation was adopted so as to not only to have the softness of reverse recovering for FWD but for reduction of turn-off losses of GCT as well.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.8
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• pp.893-897
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• 2004

In this paper, we studied the mechanical and thermal properties on slice XLPE sheet from 22 kV and 154 kV power cables. Interface structures are XLPE/semiconductor and XLPE/water/semiconductor. We evaluated mechanical property, thermal analysis, moisture analysis. Based on mechanical and thermal properties of the 22 kV XLPE sheet, elongation, mechanical strength, and melting point were evaluated to be 485.48 %, 1.74 kgf/$\textrm{mm}^2$ and $102.48^{\circ}C$, respectively. It was also evaluated from the mechanical and thermal properties of 154 kV XLPE sheet that elongation, mechanical strength, and melting point are 507.81 %, 1.8 kgf/$\textrm{mm}^2$, $106.9^{\circ}C$, respectively. A region shows a rapid increase in tension strength, and B region only shows increase in elongation under 1.0 kgf/$\textrm{mm}^2$, C region shows increase in both elongation and tension strength. Difference of melting point came from the chain of XLPE polymer and the difference of crystallization. Moisture density of semiconductor showed 800 ∼ 1200 ppm before extrude, 14000 ∼24000 ppm after extrude. These values were higher than the moisture density of XLPE (300∼560) ppm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.120-124
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• 2004

본 연구는 Diluted Ceria 입자를 사용한 $SiO_2$(Oxide) CMP 현상에 대한 내용이다. Ceria Slurry의 경우 Silica Slurry와 비교하였을 때 Oxide Wafer 표면과 축합 화학반응을 일으키며 Chemistry Dominant한 CMP Mechanism을 따르고, Wafer Center Removal Rate(RR) Fast 의 특성을 가진다. Ceria Slurry의 문제점인 연마 불균일도를 해결하기 위해 Tribological System을 이용하였다. CMP Tribology는 Pad-Slurry 유막-Wafer의 System을 가지며 윤활막에 작용하는 마찰계수(COF)가 주요 인자이다. Tribology에 적용되는 Stribeck Curve를 통해 Slurry 윤활막의 두께(h) 정도를 예상할 수 있으며, 이 윤활막의 두께를 조절함으로써 Uniformity 향상이 가능하다. 이 Ceria Slurry CMP의 연마 불균일도를 향상시킬 수 있는 방법으로 pH 조절 및 점도 증가가 있다. Ceria 입자 CMP는 분산액의 pH 변화에 강한 작용을 받게 되며 PH5 근방에서 최적화된 Uniformity가 가능하다. 점도를 증가시키는 경우 유막 h가 증가하게 되어 Ceria Slurry의 유동이 균일 분포 상태에 가까워지며 Wafer Uniformity 향상이 가능하다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.8-8
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• 2010

외부전하를 감지할 수 있는 EEPROM 구조를 기반으로 한 센서를 제안하였다. 부유게이트로부터 확장된 큰 면적의 접촉부위 (CCM)는 외부전하를 고정화하도록 설계되었으며, $0.13{\mu}m$ 단일-다결정 CMOS 공정에 적합한 적층의 금속-절연체-금속 (MIM) 제어케이트구조로 구성되었다. N-채널 EEPROM의 CCW 캐패시터 영역에 양의 전압이 인가되면 제어 게이트의 문턱전압이 음의 방향으로 변화하여 드레인 전류는 증가하는 특성을 보였다. 또한 이미 충전된 외부 캐패시터가 CCW의 부유게이트의 금속영역에 직접 연결되면, 외부 캐패시터로부터 유입된 양의 전하는 n-채널 EEPROM의 드레인 전류를 증가시키지만 반면에 음의 전하는 이를 감소시켰다. 외부 전압과 전하에 의해 PMOS의 특성은 NMOS에 비교하여 반대로 나타남이 확인되었다. EEPROM 인버터의 CCW 영역에 외부전하를 연결하면 인버터의 입-출력 특성이 기준 시료에 비해 외부전하의 극성에 따라 변화하였다. 그러므로, EEPROM 인버터는 외부전하를 감지하여 부유게이트에 고정된 전하의 밀도 크기에 따라 출력을 전압으로 표현할 수 있음을 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.8
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• pp.486-489
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• 2015

Power semiconductor device has a very long history among semiconductor, since the invention of low-pressure bipolar transistor 1947, and so far from small capacity to withstand voltage-current, high-speed and high-frequency characteristics have been developed with high function. In this study, the PWM IC Switch to the main parts used in IGBT (insulated gate bipolar transistor) for the low power loss and high drive capability of the simulator to Synopsys' T-CAD used by the 1,700 V NPT Planar IGBT, 1,700 V FS was a study of the Planar IGBT, the results confirmed that IGBT 1,700 V FS Planar is making about 11 percent less than the first designed NPT Planar IGBT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.1
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• pp.61-69
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• 2014

In this paper, we have researched semiconductor optical filters to solve the problem of the high failure rate that are recognize bad of financial account, jam of financial account and the ATM service interruption due to failure of accurate location information among the operation of the ATM (automatic teller machine) systems. A semiconductor optical filters that have high resolution and less diffuse, high transmittance are able to detect the information of financial account surface accurately. Therefore, it is a stable filter that is able to minimize the incidence of disability. In this paper, we drew the determinants by element for implement an excellent semiconductor optical filters. Based on this, we had to be able to implement the semiconductor optical filter that is able to be mounted on the actual ATM system through future studies.