• 전기학회논문지
• /
• 제58권1호
• /
• pp.199-202
• /
• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• 비파괴검사학회지
• /
• 제22권6호
• /
• pp.649-658
• /
• 2002

As an attempt to further improve the reliability and effectiveness of ultrasonic testing (UT), a two-dimensional numerical simulator of UT was developed. The simulator models the wave medium (or test object) using the mass-spring lattice model (MSLM) that consists of mass-points and springs. Some previous simulation results, obtained by using MSLM, are briefly reviewed in this paper, for propagation, reflection, and scattering of ultrasonic waves. Next, the models of transmitting and receiving piezoelectric transducers are introduced with some numerical results, which is a main focus of this paper. The UT simulator, established by combining the transducer models with the MSLM, was used to simulate many UT setups. In this paper, two simple setups are considered as examples, and their simulated A-scan signals are discussed. The potential of the MSLM, transducer models, and the UT simulator developed in this study to be used in the actual UT is confirmed.

• Nuclear Engineering and Technology
• /
• 제54권8호
• /
• pp.3043-3050
• /
• 2022

In Korea, all nuclear power plants (NPPs) participate in annual performance tests including in vivo measurements using the FastScan, a stand type whole body counter (WBC), manufactured by Canberra. In 2018, all Korean NPPs satisfied the testing criterion, the root mean square error (RMSE) ≤ 0.25, for the whole body configuration, but three NPPs which participated in an additional lung configuration test in the fission and activation product category did not meet the criterion. Due to the low resolution of the FastScan NaI(Tl) detectors, the conventional peak analysis (PA) method of the FastScan did not show sufficient performance to meet the criterion in the presence of interfering radioisotopes (RIs), ¹³⁴Cs and ¹³⁷Cs. In this study, we developed an artificial neural network (ANN) to improve the performance of the FastScan in the lung configuration. All of the RMSE values derived by the ANN satisfied the criterion, even though the photopeaks of ¹³⁴Cs and ¹³⁷Cs interfered with those of the analytes or the analyte photopeaks were located in a low-energy region below 300 keV. Since the ANN performed better than the PA method, it would be expected to be a promising approach to improve the accuracy and precision of in vivo FastScan measurement for the lung configuration.

• 비파괴검사학회지
• /
• 제36권4호
• /
• pp.273-280
• /
• 2016

비파괴검사 분야에 대한 시뮬레이션은 다양한 결함에 대한 신호의 예측과 검사 절차 개발에 사용되어진다. 특히 비파괴검사 전용 시뮬레이션 툴인 CIVA는 정확도가 높고 빠른 계산이 가능하며, 비파괴평가 기술과 동일한 형태의 화면 표시와 시각적으로 개선된 3차원 그래픽 유저 인터페이스를 제공한다. CIVA 소프트웨어 개발자가 내부적으로 타당성 검증을 시행하겠지만, 사용 이전에 소프트웨어의 정확도를 평가하는 독립적인 유효성 검증 연구가 필요하다. 이러한 목적으로 이번 연구에서는 CIVA를 이용하여 원자로 상부 헤드 관통관 검사에 사용되는 보정시험편에 대하여 TOFD 신호를 시뮬레이션하고, 실제 검사 신호와 비교하여 시뮬레이션 신호의 정확도와 적용 범위에 대하여 검증하였다. 종합적으로, A-scan 신호, B-scan 이미지, 깊이 측정 측면에서 CIVA 시뮬레이션 결과와 실험 결과 간에 전반적으로 일치를 보였다.

• 한국정보통신학회논문지
• /
• 제14권1호
• /
• pp.225-232
• /
• 2010

용접부 내에 존재하는 결함의 형태, 위치, 크기 등의 정보를 정량적으로 파악하기 위하여 초음파 탐상 검사가 많이 활용되는데, 최근 들어 용접부의 결함 탐상을 위해, 검사과정을 기계적 스캐너로 자동화한 자동 초음파 탐상 시스템이 많은 산업 분야에서 활용되고 있고, 특히 배관 용접부의 건전성 평가를 위한 비파괴안전진단에서 그 활용 폭이 커지고 있다. 본 논문에서는 배관 용접부의 자동 초음파 검사를 위한 알고리즘 구현과 결함 영상을 보정하여 주는 결함영상 처리 시스템을 설계 및 구현하였다. 적용된 기법으로는 초음파 A-Scan 압축 알고리즘, Synthetic Aperture Focusing 알고리즘, 결함영상증폭 알고리즘과 이와 관련된 소프트웨어 설계 및 구현에 대하여 논한다.

• 비파괴검사학회지
• /
• 제24권4호
• /
• pp.348-353
• /
• 2004

이 연구는 터빈베어링의 신뢰성을 평가하기 위하여 초음파 C-Scan 방법을 적용한 기술이다. 수침법에 관한 연구는 실험실과 현장검사 적용에 광범위하게 사용되는 기술이다. 여기에서는 C-Scan 방법을 이용하여 베어링의 모재와 Babbitt 금속간 경계부의 상태를 평가하였다. 수침법 C-Scan 방법에 의한 초음파 영상은 베어링 경계부의 상태를 확인하는데 효과적인 방법으로 사용될 수 있었다. 초음파 영상의 분해능을 높이기 위하여 집속형 탐촉자를 사용하고, Babbitt 금속과 베어링 모재간의 접합경계면에서 발생하는 초음파 음압 반사율을 측정하여 결함의 검출과 면적을 추정할 수 있었다. 초음파 수침법은 베어링 접합부의 박리위치와 박리면적의 경계면을 결정하여 크기를 계산하는데 아주 유용하게 사용될 수 있는 기술이며, 이 연구에서 개발된 기술은 화력발전소에서 사용되고 있는 터빈베어링의 건전성을 확보하는데 적용되었다.

• 한국신뢰성학회지:신뢰성응용연구
• /
• 제16권4호
• /
• pp.338-346
• /
• 2016

Purpose: The purpose of this research is to improve the reliability of the composite material blades used for the wind power generator, by applying the phased array ultrasonic testing technique out of the many nondestructive test into the blades. Method: The wind power generation composite blades are used, as a case study, in order to evaluate the reliability of the phased array ultrasonic testing technique. Defects that are most likely occurred in the field are injected into the different locations of the three different types of artificial test pieces and then phased array ultrasonic testing technique are applied to evaluate the reliability of its effectiveness. Result: As a result of the analysis of the defect signals by applying the A scan and B scan simultaneously, depth and width of the defect could be obtained. An area of defect was proportional to the amount of energy by color in B scan image. The larger amount of energy, reflected amount of energy was appeared in the order of red, orange, yellow, blue color. Conclusion: The most reliable testing method to detect the defect in composite blades for wind power generation is considered to be the combination of the other destructive testing technique with the phased array ultrasonic testing since the PAUT alone could not detect all range of the defects in the blades.

• 전기학회논문지
• /
• 제56권5호
• /
• pp.980-986
• /
• 2007

Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits.

• 비파괴검사학회지
• /
• 제10권2호
• /
• pp.32-37
• /
• 1990

A computer controlled 5 axis ultrasonic testing system is developed in order to detect flaws in special parts with complex shape. The various kinds of ultrasonic test can be performed automatically using computer program which was developed by DHI(Daewoo Heavy Industries Ltd.). By use of this computer program, the detector location can be programed and the amplitude signal of echo can be processed digitally. The test results can be plotted graphically on a high resolution display monitor in real time base. The test data can be also saved in magnetic memory devices(HDD or FDD) as well as in the form of hard copy through color printer. The computer software contains c- scan, c+a scan processing programs as well as statistical analysis for test data.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권5호
• /
• pp.640-648
• /
• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.