• Title/Summary/Keyword: scan design

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Two Degree of Freedom Robust Controller Design of a Seeker Scan-Loop (탐색기 주사루프의 2자유도 강인제어기 설계)

  • Lee, Ho-Pyeong;Song, Chang-Seop
    • Journal of the Korean Society for Precision Engineering
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    • v.12 no.10
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    • pp.157-165
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    • 1995
  • The new formulation of designing the two degree of freedom(TDF) robust controller is proposed using $H_{\infty}$optimization and model matching method. In this formulation the feedback controller and feedforward controller are designed in a single step using $H_{\infty}$optimization procedure. Roughly speaking, the feedback controller is designed to meet robust stability and disturbance rejection specifications, while the feedforward controller is used to improve the robust model matching properties of the closed loop system. The proposed formulation will be illustrated and evaluated on a seeker scan-loop. And the performances of TDF robust controller are compared with those of the $H_{\infty}$ controller designed using Loop Shaping Design Procedure proposed by McFarlane and Glover.lover.

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Image Enhancement Techniques for UT - NDE for Sizing and Detection of Cracks in Narrow Target (초음파 비파괴 평가를 위한 협소 타깃의 크랙 사이징 및 검출을 위한 영상 증진기술)

  • Lee, Young-Seock;Nam, Myoung-Woo;Hong, Sunk-Wan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.8 no.2
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    • pp.245-249
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    • 2007
  • In this paper describes image enhancement technique using deconvolution processing for ultrasonic nondestructive testing. When flaws are detected fur B-scan or C-scan, blurring effect which is caused by the moving intervals of transducer degrades the quality of images. In addition, acquisited images suffer form speckle noise which is caused by the ultrasonic components reflected from the grain boundary of material (1,2). The deconvolution technique can restore sharp peak value or clean image from blurring signal or image. This processing is applied to C-scan image obtained from known specimen. Experimental results show that the deconvolution processing contributes to get improved the quality of C-scan images.

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Usability verification of virtual clothing system for the production of a 3D avatar reproduced from 3D human body scan shape data - Focusing on the CLO 3D program - (3차원 인체스캔형상을 재현한 3D 아바타 제작을 위한 가상착의 시스템의 활용성 검증 -CLO 3D 프로그램을 중심으로-)

  • Hong, Eun-Hee
    • Journal of the Korea Fashion and Costume Design Association
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    • v.22 no.1
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    • pp.1-13
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    • 2020
  • The purpose of this study is to create a 3D avatar from 3D human body shape data using the CLO 3D virtual clothing program and to verify the feasibility of avatar production using the virtual clothing system for verifying size and shape. The research method was to select one virtual representative model that is the closest to the mean size of each body item for each age group. Using the 3D human body scan shape of a 40-69 years old male was applied to the CLO 3D virtual wearing system. Using the CLO 3D Avatar conversion menu, we verified the feasibility of creating a 3D avatar that reproduces the human body scan shape. In the dimension comparison between the 3D avatar and the fictitious representative model, the dimension difference was noticeable in height, circumference, and length. However, as a result, the converted 3D avatar showed less than a 5% difference in most human dimensions. In addition, since the body shape and posture were reproduced similarly, the utilization of the avatar was verified.

Reduction of Test Data and Power in Scan Testing for Digital Circuits using the Code-based Technique (코드 기반 기법을 이용한 디지털 회로의 스캔 테스트 데이터와 전력단축)

  • Hur, Yong-Min;Shin, Jae-Heung
    • 전자공학회논문지 IE
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    • v.45 no.3
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    • pp.5-12
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    • 2008
  • We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

Design and implementation of port scan detection improvement and algorithm connected with attack detection in IDS (침입탐지시스템에서 포트 스캔 탐지 개선 및 공격 탐지와 연계한 알고리즘 설계 및 구현)

  • Park Seong-Chul;Ko Han-Seok
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.16 no.3
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    • pp.65-76
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    • 2006
  • This paper deals with an effective algerian aimed at improving the port scan detection in an intrusion detection system (IDS). In particular, a detection correlation algerian is proposed to maximize the detection capability in the network-based IDS whereby the 'misuse' is flagged for analysis to establish intrusion profile in relation to the overall port scan detection process. In addition, we establish an appropriate system maintenance policy for port scan detection as preprocessor for improved port scan in IDS, thereby achieving minimum false positive in the misuse detection engine while enhancing the system performance.

Estimation In-Situ Rockfall Block Weight Distribution Using Scan-Line Survey Results and Examination its applicability in Practical Rockfall Analysis (선조사 결과에 의한 실제낙석무게분포의 추정과 설계적용성 검토)

  • Kim, Su-Chul;Kim, Dong-Hee;Jung, Hyuk-Il;Kim, Seok-Ki
    • Proceedings of the Korean Geotechical Society Conference
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    • 2005.10a
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    • pp.639-648
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    • 2005
  • Up to now, practical engineers applying simplicity value of rockfall block weight suggested in design manual without considering in-situ rockfall block weight which reflect joint characteristics. However, the size of rockfall block varies with joint spacing of discontinuities and influences over rockfall analysis results. In this paper, we estimate realistic rockfall block weight distribution using statistical invariances of joint spacing derived from scan-line survey result. And, we study whether this distribution is applicable in practical rockfall analysis directly. As the results of this study, rockfall analysis results that using rockfall block weight distribution estimated from scan-line survey show resonable and realistic outcomes.

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Suggestion of OSMU Content New Business Market through Development of Integrated Platforms for Software-oriented Tailored Costume Production (소프트웨어 중심의 주문 형 의상제작 융합플랫폼 개발을 통한 OSMU콘텐츠 뉴비즈니스 시장 창출 제안)

  • Jung, Minsoo
    • Journal of Korea Multimedia Society
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    • v.21 no.8
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    • pp.1021-1026
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    • 2018
  • 3D SCAN enables easy human body measurement via a digital method in the process of film costume production which used to be done manually. Software-oriented computer graphic, which integrates 3D SCAN data in the process of manual film costume production, can induce quick and diverse design outcomes. While, 3D PRINT, which integrates computer graphic data in the process of manual film costume production, can automate the process of special costume production using a digital method. Integration of 3D Scan + Computer Graphic + 3D Print using integrated platforms for tailored costume production as developed in this study allows significant reduction of costume production period and costs. It also allows efficient integration of costume production outcomes in various industries related with OSMU contents in particular. In other words, using it, we can create a new business market that integrates multiple areas of film content, drama content and game content.

Design and Simulation of Edge Painting Machine for Image Rasterization (Image rasterization을 위한 Edge Painting Machine의 설계 및 simulation)

  • Choi, Sang-Gil;Kim, Sung-Soo;Eo, Kil-Su;Kyung, Chong-Min
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1492-1494
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    • 1987
  • This paper describes a hardware architecture called Edge Painting Machine for real time generation of scan line images for raster scan graphics display. The Edge Painting Machine consists of Scanline Processor which converts polygon data sorted in their depth priority into a set of scan line commands for each scan line, and Edge Painting Tree which converts the scanline commands set into a raster line image. Edge painting tree has been designed using combinational logic circuit. The designed circuit has been simulated to verify the proper functioning. A salient feature of the EPT is that hardware composition is simple, because each processor is constituted by only combinational logic circuit.

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The Design of Optical Marker for Auto-registering of 3D scan data (3차원 스캐너의 레지스터링 문제 해결을 위한 광학식 마커 설계)

  • 손용훈;양현석
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2003.06a
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    • pp.256-259
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    • 2003
  • This paper proposes OPTICAL MARKER fer registering process - one of the 3D measurement process : scan registering - merging - measurement. If the registering work is carried out manually, it can be accompanied with much time and many errors. Because the patterned marker make registering process automatic, many firms use it now. But the physical shape of existing markers is the source of the data loss caused by hiding surface, and the marker arrangement is the source of the time loss. The optical marker proposed in this paper has marker generator, organized a large number of binary coded control laser diode, separate from 3D scan object. So, it does not take much time for the marker disposition, and it is not the origin of the data loss, and the binary coded laser information make the auto-registering possible.

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Design for Lour pouter Scan-based BIST Using Circuit Partition and Control Test Input Vectors (회로분할과 테스트 입력 벡터 제어를 이용한 저전력 Scan-based BIST 설계)

  • 신택균;손윤식;정정화
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.125-128
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    • 2001
  • In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

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