• The Transactions of the Korea Information Processing Society
• /
• v.3 no.7
• /
• pp.1924-1937
• /
• 1996

In this paper, we propose a ESP(Extended Scan Path) architecture for multi- board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan paths either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using, he proposed ESP architecture, we observed to the test time is short compared with the single scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS '85 bench mark circuit, we showed that the architecture has improved results.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.127-138
• /
• 2007

In this paper, we propose a new X-masking scheme for utilizing logic built-in self-test The new scheme exploits the phase-shifting network which is based on the shift-and-add property of maximum length pseudorandom binary sequences(m-sequences). The phase-shifting network generates mask-patterns to multiple scan chains by appropriately shifting the m-sequence of an LFSR. The number of shifts required to generate each scan chain mask pattern can be dynamically reconfigured during a test session. An iterative simulation procedure to synthesize the phase-shifting network is proposed. Because the number of candidates for phase-shifting that can generate a scan chain mask pattern are very large, the proposed X-masking scheme reduce the hardware overhead efficiently. Experimental results demonstrate that the proposed X-masking technique requires less storage and hardware overhead with the conventional methods.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1205-1208
• /
• 2003

본 논문에서는 분할된 스캔을 이용한 저전력 BIST 구조를 제안한다. 제안하는 BIST는 내부 스캔 패스를 회로의 구조적인 정보와 테스트 패턴 집합의 특성에 따라 4개의 스캔 패스로 분할하고 일부 스캔 패스에만 입력패턴이 인가되도록 설계하였다. 따라서 테스트 패턴 입력 시에 스캔 패스로의 쉬프트 동작 수를 줄임으로써 회로 내부의 전체 상태천이 수를 줄일 수 있다. 또한 4개로 분할되는 스캔패스의 길이를 고려하여 각 스캔 패스에 대해 1/4의 속도로 낮춰진 테스트 클럭을 인가함으로써 전체 회로의 전력 소모를 줄일 수 있도록 하였다. ISCAS89 벤치마크 회로에 대한 실험을 통하여 제안하는 BIST 구조가 기존 BIST 구조에 비해 최대 21%까지 전력소모를 줄일 수 있음을 확인하였다.

• Journal of Biosystems Engineering
• /
• v.17 no.2
• /
• pp.143-155
• /
• 1992

The aim of this study is to develop a general purpose algorithm for analyzing geometrical features of agricultural products and microscopic particles regardless of their numbers, shapes and positions with a computer vision system. Primarily, boundary informations of an image were obtained by Scan Line Coding and Scan & Chain Coding methods and then with these informations, geometrical features such as area, perimeter, lengths, widths, centroid, major and minor axes, equivalent circle diameter, number of individual objects, etc, were analyzed. The algorithms developed in this study was evaluated with test images consisting of a number of randomly generated ellipsoids or a few synthesized diagrams having different features. The result was successful in terms of accuracy.

• KSTLE International Journal
• /
• v.6 no.1
• /
• pp.13-16
• /
• 2005

Friction characteristics at nano-scale of self-assembled monolayers (SAMs) having different chain lengths and end groups were experimentally studied.51 order to understand the effect of the chain length and end group on the nano-scalefriction: (1) two different SAMs of shorter chain lengths with different end groups such as methyl and phenyl groups, and (2)four different kinds of SAMs having long chain lengths (C10) with end groups of fluorine and hydrogen were coated on siliconwafer (100) by dipping method and Chemical Vapour Deposition (CVD) technique. Their nano-scale friction was measuredusing an Atomic Force Microscopy (AFM) in the range of 0-40 nN normal loads. Measurements were conducted at the scanning speed of 2 $mu$m/s for the scan size of 1$mu$m x 1 $mu$m using a contact mode type $Si_3N_4$ tip (NPS 20) that had a nominal spring constant0.58 N/m. All experiments were conducted at anlbient temperature (24 $pm$1$circ$C) and relative humidity (45 $pm$ 5%). Results showedthat the friction force increased with applied normal load for all samples, and that the silicon wafer exhibited highest frictionwhen compared to SAMs. While friction was affected by the inherent adhesion in silicon wafer, it was influenced by the chainlength and end group in the SAMs. It was observed that the nano-friction decreased with the chain length in SAMs. In the caseof monolayers with shorter length, the one with the phenyl group exhibited higher friction owing to the presence of benBenerings that are stiffer in nature. In the case of SAMs with longer chain length, those with fluorine showed friction values relativelyhigher than those of hydrogen. The increase in friction due to the presence of fluorine group has been discussed with respect tothe siBe of the fluorine atom.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.29B no.9
• /
• pp.50-58
• /
• 1992

A new algorithm for filling the interior of contours and labelling each filled region concurrently is presented. Filling is simply accomplished by inversion method. The labelling information in every scan lines is extracted directly from current direction of chain code so that the proposed algorithm needs less comparision and is more efficient. The contours are followed by two different directions, clockwise for the outer contour and counterclockwise for the inner contour to get filling and labelling information. This algorithm can be applied in case that contours are nested or regions are continous. Simulataneously the proposed algorithm can find the structure tree of object without additional post processing.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.723-728
• /
• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• Proceedings of the KAIS Fall Conference
• /
• 2008.05a
• /
• pp.189-191
• /
• 2008

본 논문에서는 스캔 체인의 레이아웃 거리를 고려한 효율적인 Test Wrapper 설계 방식을 제안한다. SoC내의 스캔체인들을 테스트 하기 위해서는 외부 TAM line에 각 스캔체인들을 할당해야 한다. IP 내에 존재하는 스캔체인들은 스캔체인간 레이아웃 거리를 갖게 되며 이 거리가 클럭주기를 넘어가는 경우 체인의 타이밍 위반(Timing violation)이 발생될 수 있다. 본 논문에서는 타이밍 위반이 발생하지 않도록 체인간 거리를 고려하여 스캔체인을 할당하는 새로운 test wrapper 설계 방식을 제안하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.26-31
• /
• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• Pediatric Gastroenterology, Hepatology & Nutrition
• /
• v.19 no.2
• /
• pp.143-146
• /
• 2016

Pediatric mesenteric panniculitis is an extremely rare disease of unknown etiology characterized by chronic inflammation, fat necrosis, and fibrosis in the mesenteric adipose tissue. A previously healthy 13-year-old boy was admitted because of right upper abdominal pain. An abdominal computed tomography scan revealed increased attenuation and enhancement in the left upper abdominal omental fat and anterior peritoneal wall thickening. A laparoscopic biopsy showed mesenteric panniculitis with chronic inflammation, adiponecrosis, and septal fibrosis. Serological tests for autoimmune diseases, nested polymerase chain reaction for Mycobacterium tuberculosis, and special immunohistochemical stains for malignancy were all negative. Symptomatic improvement and improved abnormal findings were achieved after an 8-month treatment with prednisolone according to a follow-up abdominal computed tomography scan. Here, we report a case of pediatric mesenteric panniculitis treated with prednisolone.