• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.523-524
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• 2006

Successive approximation A/D converters have an advantage of small chip area and simple algorithm. We propose an improved non-redundant successive approximation register (SAR) which can be incorporated in successive approximation A/D converters. The proposed SAR validates the preset state as the $1^{st}$ reference voltage to the comparator. Two redundant clock cycles in the typical design could be eliminated in the proposed A/D converter.

• 한국전기전자재료학회논문지
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• 제17권2호
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• pp.144-149
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• 2004

Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

• 대한임베디드공학회논문지
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• 제5권1호
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• pp.18-22
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• 2010

In real-time embedded systems, the responsibility is the most important thing because it is related to human life. Context switching is a part of which can slow down the responsibility. We therefore should minimize the amount of state that needs to be saved during context switching. In this paper, we introduce a new architecture (Register Farm) for context switching which can exchange two contexts in one cycle time. Although it might increase the cost of MCU design and the complexity of circuit, it cannot miss any interrupt during context switching. Consequently, Register Farm architecture can make embedded systems spread out in human life because it can increase reliability and responsibility in real time embedded systems.

• 전기학회논문지P
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• 제59권4호
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• pp.401-404
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• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

• 한국컴퓨터정보학회논문지
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• 제5권3호
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• pp.1-8
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• 2000

선코드 스케줄링은 코드 스케줄링을 먼저 수행함으로써 자료 종속 관계가 복잡해지고. 레지스터를 할당할 때 간섭그래프가 복잡해져 레지스터 할당을 어렵게 만들 수 있다. 본 논문에서는 이를 개선하기 위하여 2-단계 컬러링 기법을 제안한다. 단계 1에서 생존 거리가 큰 변수들에 레지스터 배정, 단계 2에서 나머지 변수들에 레지스터를 할당함으로써 레지스터 할당 소요 비용을 최소화한다. 실험 결과 기존의 방법에 비해 제안한 방법이 효율적임을 검증하였다.

• Journal of applied mathematics & informatics
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• 제39권5_6호
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• pp.859-882
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• 2021

In the proposed paper, a new algorithm based on Nonlinear Feedback Shift Register (NLFSR) and modified RC4A (Rivest Cipher 4A) cipher is introduced. NLFSR is used for image pixel scrambling while modified RC4A algorithm is used for pixel substitution. NLFSR used in this algorithm is of order 27 with maximum period 2^27-1 which was found using Field Programmable Gate Arrays (FPGA), a searching method. Modified RC4A algorithm is the modification of RC4A and is modified by introducing non-linear rotation operator in the Key Scheduling Algorithm (KSA) of RC4A cipher. Analysis of occlusion attack (up to 62.5% pixels), noise (salt and pepper, Poisson) attack and key sensitivity are performed to assess the concreteness of the proposed method. Also, some statistical and security analyses are evaluated on various images of different size to empirically assess the robustness of the proposed scheme.

• ETRI Journal
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• 제43권5호
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• pp.900-908
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• 2021

This paper proposes thermometer-code latches having five and six transistors for unidirectional and bidirectional thermometer-code shift-registers, respectively. The proposed latches omit the set and reset transistors by changing from two supply voltage nodes to the set and reset signals in the cross-coupled inverter. They set or reset the data by changing the supply voltage to ground in either of two inverters. They reduce the number of transistors to five and six compared with the conventional thermometer-code latches having six and eight transistors, respectively. The proposed thermometer-code latches were simulated using a 65 nm complementary metal-oxide-semiconductor (CMOS) process. For comparison, the proposed and conventional latches are adapted to the 64 bit thermometer-code shift-registers. The proposed unidirectional and bidirectional shift-registers occupy 140 ㎛² and 197 ㎛², respectively. Their consumption powers are 4.6 ㎼ and 5.3 ㎼ at a 100 MHz clock frequency with the supply voltage of 1.2 V. They decrease the areas by 16% and 13% compared with the conventional thermometer-code shift-register.

• Journal of Advanced Research in Ocean Engineering
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• 제4권4호
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• pp.204-216
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• 2018

A ship repeatedly face free surface under rough sea conditions owing to relative motion with wave encounter. The impact pressure is transferred to the hull structure and causes structural damage. In this study, the bow flare slamming load of a container ship is estimated using computations fluid dynamics (CFD) and prescript formula according to various classifications. It is found that the bow flare slamming load calculated by the formulas of the common structural rule and ABS tends to be similar to the CFD results.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2019년도 춘계학술대회
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• pp.19-21
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• 2019

본 논문에서는 VDES 시스템과 해상 통신용 다중경로 채널 모델을 소개하고, 다중경로 환경이 비트오률(BER)성능에 미치는 영향을 모의 시험을 통해 분석한다. 또한 다중경로 환경에 대응할 수 있는 방안으로 시간영역 적응형 등화기 적용을 제안하고, 그 결과를 검토하여 적응형 등화기 적용의 필요성에 대하여 확인하도록 한다.

• 대한조선학회논문집
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• 제56권3호
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• pp.242-250
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• 2019

The speed and power performance of a ship is not only a guarantee issue between the ship owner and the ship-yard, but also is related with the Energy Efficiency Design Index (EEDI) regulation. Recently, International Organization for Standardization (ISO) published the procedure of the measurement and assessment for ship speed and power at sea trial. The results of speed and power performance measured in actual sea condition must inevitably include various uncertainty factors. In this study, the influence for systematic error of shaft power measurement system was examined using the Monte Carlo simulation. It is found that the expanded uncertainty of speed and power performance is approximately ${\pm}1.2%$ at the 95% confidence level(k=2) and most of the uncertainty factor is attributed to shaft torque measurement system.