• Title/Summary/Keyword: reflow bonding

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Effect of Sn Decorated MWCNT Particle on Microstructures and Bonding Strengths of the OSP Surface Finished FR-4 Components Assembled with Sn58%Bi Composite Solder Joints (OSP 표면처리된 FR-4 PCB기판과 Sn58%Bi 복합솔더 접합부의 미세조직 및 접합강도에 미치는 Sn-MWCNT의 영향)

  • Park, Hyun-Joon;Lee, Choong-Jae;Min, Kyung Deuk;Jung, Seung-Boo
    • Journal of the Microelectronics and Packaging Society
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    • v.26 no.4
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    • pp.163-169
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    • 2019
  • Sn-Pb solder alloys in electronics rapidly has been replaced to Pb free solder alloys because of various environmental regulations such as restriction of hazardous substances directive (RoHS), European Union waste electrical, waste electrical and electronic equipment (WEEE), registration evaluation authorization and of chemicals (REACH) etc. Because Sn58%Bi (in wt.%) solder alloy has low melting point and higher mechanical properties than that of Sn-Pb solder, it has been studied to manufacture electronic components. However, the reliability of Sn58%Bi solder could be lowered because of the brittleness of Bi element included in the solder alloy. Therefore, we observed the microstructures of Sn58%Bi composite solders with various contents of Sn-decorated multiwalled carbon nanotube (Sn-MWCNT) particles and evaluated bonding strength of the FR-4 components assembled with Sn58%Bi composite solder. Also, microstructures and bonding strengths of the Sn58%Bi composite solder joints were evaluated with the number of reflows from 1 to 7 times, respectively. Bonding strengths and fracture energies of the Sn58%Bi composite solder joints were measured by die shear test. Microstructures and fracture modes were observed with scanning electron microscope (SEM). Microstructures in the Sn58%Bi composite solder joints were finer than that of only Sn58%Bi solder joint. Bonding strength and fracture energy of Sn58%Bi composite solder including 0.1 wt.% of Sn-decorated MWCNT particles increased up to 20.4% and 15.4% at 5 times in reflow, respectively.

A Study of Warpage Analysis According to Influence Factors in FOWLP Structure (FOWLP 구조의 영향 인자에 따른 휨 현상 해석 연구)

  • Jung, Cheong-Ha;Seo, Won;Kim, Gu-Sung
    • Journal of the Semiconductor & Display Technology
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    • v.17 no.4
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    • pp.42-45
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    • 2018
  • As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

Cap Formation Process for MEMS Packages using Cu/Sn Rim Bonding (Cu/Sn Rim 본딩을 이용한 MEMS 패키지의 Cap 형성공정)

  • Kim, S.K.;Oh, T.S.;Moon, J.T.
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.4
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    • pp.31-39
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    • 2008
  • To develop the MEMS cap bonding process without cavity formation, we electroplated Cu/Sn rim structures and measured the bonding characteristics for the Cu/Sn rims of $25{\sim}400{\mu}m$ width. As the effective device-mounting area ratio decreased and the failure strength ratio increased for wider Cu/Sn rim, these two properties were estimated to be optimized for the Cu/Sn rim with 150 ${\mu}m$ width. Complete bonding was accomplished at the whole interfaces of the Cu/Sn packages with the rim widths of 25 ${\mu}m$ and 50 ${\mu}m$. However, voids were observed locally at the interfaces with the rim widths larger than 100 ${\mu}m$. Such voids were formed by local non-contact between the upper and lower rims due to the surface roughness of the electroplated Sn.

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Evaluation of Bonding Properties of Epoxy Solder Joints by High Temperature Aging Test (고온 시효 시험에 따른 Epoxy 솔더 접합부의 접합 특성 평가)

  • Kang, Min-Soo;Kim, Do-Seok;Shin, Young-Eui
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.32 no.1
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    • pp.6-12
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    • 2019
  • Bonding properties of epoxy-containing solder joints were investigated by a high temperature aging test. Specimens were prepared by bonding an R3216 standard chip resistor to an OSP-finished PCB by a reflow process with two basic types of solder (SAC305 & Sn58Bi) pastes and two epoxy-solder (SAC305+epoxy & Sn58Bi+epoxy) pastes. In all epoxy solder joints, an epoxy fillet was formed in the hardened epoxy, lying around the outer edge of the solder joint, between the chip and the Cu pad. In order to analyze the bonding characteristics of solder joints at high temperatures, a high-temperature aging test at $150^{\circ}C$ was carried out for 14 days (336 h). After aging, the intermetallic compound $Cu_6Sn_5$ was found to have formed in the solder joint on the Cu pad, and the shear stress on the conventional solder joint was reduced by a significant amount. The reason that the shear force did not decrease much, even though in epoxy solder, was thatbecause epoxy hardened at the outer edge of the supported solder joints. Using epoxy solder, strong bonding behavior can be ensured due to this resistance to shear force, even in metallurgical changes such as those where intermetallic compounds form at solder joints.

Epoxy-based Interconnection Materials and Process Technology Trends for Semiconductor Packaging (반도체 패키징용 에폭시 기반 접합 소재 및 공정 기술 동향)

  • Eom, Y.S.;Choi, K.S.;Choi, G.M.;Jang, K.S.;Joo, J.H.;Lee, C.M.;Moon, S.H.;Moon, J.T.
    • Electronics and Telecommunications Trends
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    • v.35 no.4
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    • pp.1-10
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    • 2020
  • Since the 1960s, semiconductor packaging technology has developed into electrical joining techniques using lead frames or C4 bumps using tin-lead solder compositions based on traditional reflow processes. To meet the demands of a highly integrated semiconductor device, high reliability, high productivity, and an eco-friendly simplified process, packaging technology was required to use new materials and processes such as lead-free solder, epoxy-based non cleaning interconnection material, and laser based high-speed processes. For next generation semiconductor packaging, the study status of two epoxy-based interconnection materials such as fluxing and hybrid underfills along with a laser-assisted bonding process were introduced for fine pitch semiconductor applications. The fluxing underfill is a solvent-free and non-washing epoxy-based material, which combines the underfill role and fluxing function of the Surface Mounting Technology (SMT) process. The hybrid underfill is a mixture of the above fluxing underfill and lead-free solder powder. For low-heat-resistant substrate applications such as polyethylene terephthalate (PET) and high productivity, laser-assisted bonding technology is introduced with two epoxy-based underfill materials. Fluxing and hybrid underfills as next-generation semiconductor packaging materials along with laser-assisted bonding as a new process are expected to play an active role in next-generation large displays and Augmented Reality (AR) and Virtual Reality (VR) markets.

Thermal Shock Cycles Optimization of Sn-3.0 Ag-0.5 Cu/OSP Solder Joint with Bonding Strength Variation for Electronic Components (Sn-3.0 Ag-0.5 Cu/OSP 무연솔더 접합계면의 접합강도 변화에 따른 전자부품 열충격 싸이클 최적화)

  • Hong, Won-Sik;Kim, Whee-Sung;Song, Byeong-Suk;Kim, Kwang-Bae
    • Korean Journal of Materials Research
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    • v.17 no.3
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    • pp.152-159
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    • 2007
  • When the electronics are tested with thermal shock for Pb-free solder joint reliability, there are temperature conditions with use environment but number of cycles for test don't clearly exist. To obtain the long term reliability data, electronic companies have spent the cost and times. Therefore this studies show the test method and number of thermal shock cycles for evaluating the solder joint reliability of electronic components and also research bonding strength variation with formation and growth of intermetallic compounds (IMC). SMD (surface mount device) 3216 chip resistor and 44 pin QFP (quad flat package) was utilized for experiments and each components were soldered with Sn-40Pb and Sn-3.0 Ag-0.5 Cu solder on the FR-4 PCB(printed circuit board) using by reflow soldering process. To reliability evaluation, thermal shock test was conducted between $-40^{\circ}C\;and\;+125^{\circ}C$ for 2,000 cycles, 10 minute dwell time, respectively. Also we analyzed the IMCs of solder joint using by SEM and EDX. To compare with bonding strength, resistor and QFP were tested shear strength and $45^{\circ}$ lead pull strength, respectively. From these results, optimized number of cycles was proposed with variation of bonding strength under thermal shock.

Warpage Characteristics of Bottom Packages for Package-on-Package(PoP) with Different Chip Mounting Processes (칩 실장공정에 따른 Package on Package(PoP)용 하부 패키지의 Warpage 특성)

  • Jung, D.M.;Kim, M.Y.;Oh, T.S.
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.3
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    • pp.63-69
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    • 2013
  • The warpage of a bottom package of Package on Package(PoP) where a chip was mounted to a substrate by flip chip process was compared to that of a bottom package for which a chip was bonded to a substrate using die attach film(DAF). At the solder reflow temperature of $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpages of $57{\mu}m$ and $-102{\mu}m$, respectively. At the temperature range between room temperature and $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpage values ranging from $-27{\mu}m$ to $60{\mu}m$ and from $-50{\mu}m$ to $-15{\mu}m$, respectively.

Reflow Behavior and Board Level BGA Solder Joint Properties of Epoxy Curable No-clean SAC305 Solder Paste (에폭시 경화형 무세정 SAC305 솔더 페이스트의 리플로우 공정성과 보드레벨 BGA 솔더 접합부 특성)

  • Choi, Han;Lee, So-Jeong;Ko, Yong-Ho;Bang, Jung-Hwan;Kim, Jun-Ki
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.1
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    • pp.69-74
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    • 2015
  • With difficulties during the cleaning of reflow flux residues due to the decrease of the part size and interconnection pitch in the advanced electronic devices, the need for the no-clean solder paste is increasing. In this study, an epoxy curable solder paste was made with SAC305 solder powder and the curable flux of which the main ingredient is epoxy resin and its reflow solderability, flux residue corrosivity and solder joint mechanical properties was investigated with comparison to the commercial rosin type solder paste. The fillet shape of the cured product around the reflowed solder joint revealed that the curing reaction occurred following the fluxing reaction and solder joint formation. The copper plate solderability test result also revealed that the wettability of the epoxy curable solder paste was comparable to those of the commercial rosin type solder pastes. In the highly accelerated temperature and humidity test, the cured product residue of the curable solder paste showed no corrosion of copper plate. From FT-IR analysis, it was considered to be resulted from the formation of tight bond through epoxy curing reaction. Ball shear, ball pull and die shear tests revealed that the adhesive bonding was formed with the solder surface and the increase of die shear strength of about 15~40% was achieved. It was considered that the epoxy curable solder paste could contribute to the improvement of the package reliability as well as the removal of the flux residue cleaning process.

Wafer level vertical interconnection method for microcolumn array (마이크로컬럼 어레이에 적용 가능한 웨이퍼단위의 수직 배선 방법)

  • Han, Chang-Ho;Kim, Hyeon-Cheol;Kang, Moon-Koo;Chun, Kuk-Jin
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.793-796
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    • 2005
  • In this paper, we propose a method which can improve uniformity of a miniaturized electron beam array for inspection of very small pattern with high speed using vertical interconnection. This method enables the individual control of columns so that it can reduce the deviation of beam current, beam size, scan range and so on. The test device that used vertical interconnection method was fabricated by multiple wafer bonding and metal reflow. Two silicon and one glass wafers were bonded and metal interconnection by melting of electroplated AuSn was performed. The contact resistance was under $10{\Omega}$.

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A Study on Fluxless Soldering using Solder Foil (솔더 포일을 이용한 무플럭스 솔더링에 관한 연구)

  • 신영의;김경섭
    • Journal of Welding and Joining
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    • v.16 no.5
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    • pp.100-107
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    • 1998
  • This paper describes fluxless soldering of reflow soldering process using solder foil instead of solder pastes. There is an increasing demand for the reliable solder connection in the recent high density microelectronic components technologies. And also, it is problem fracture of an Ozone layer due to freon as which is used to removal of remained flux on the substrate. This paper discussed joining phenomena, boudability and joining processes of microelectronics devices, such as between outer lead of VLSI package and copper pad on a substrate without flux. The shear strength of joints is 8 to 13 N using Sn/Pb (63/37 wt.%) solder foil with optimum joining conditions, meanwhile, in case of using Sn/In (52/48 wt.%) solder foil, it is possible to bond with low heating temperature of 550 K, and accomplish to high bonding strength of 25N in condition heating temperature of 650K. Finally, this paper experimentally shows fluxless soldering using solder foil, and accomplishes key technology of microsoldering processes.

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