• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• Information and Communications Magazine
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• v.23 no.7
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• pp.38-46
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• 2006

• The Magazine of the IEIE
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• v.34 no.8
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• pp.50-56
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• 2007

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.5
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• pp.251-258
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• 2014

This paper proposes an efficient token flow design methodology for a decoder in the MPEG Reconfigurable Media Coding (RMC) framework. The MPEG RMC framework facilitates a decoder to be configured with a set of modules called functional units (FUs) that are connected by tokens. Such a modular design philosophy of the MPEG RMC framework enables the reusability and reconfigurability of FUs. One drawback of the MPEG RMC framework is that the decoder performance can be affected by increasing the token transmissions between FUs. The proposed method improves the design of the FU network in the RMC framework toward real-time decoder implementation. In the proposed method, the merging of FU, the separation of token flow, and the merging of token transactions are applied to minimize the token traffic between FUs. The experimental results of the MPEG-4 SP decoder show that the proposed method reduces the total decoding time by up to 77 percent compared to the design of the RMC simulation model.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.1-12
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• 1993

A multiprocessor system for high-speed processing of hybrid image coding algorithms such as H.261, MPEG, or Digital HDTV is presented in this study. Using a combination of highly parallel 32-bit microprocessor, DCT(Discrete Cosine Transform), and motion detection processor, a new processing module is designed for the implementation of high performance coding system. The sysyem is implemented to allow parallel processing since a single module alone cannot perform hybrid coding algorithms at high speed, and crossbar switch is used to realize various parallel processing architectures by altering interconnections between processing modules within the system.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.65-68
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• 2002

The verification of software part and HW/SW interface suffer from the absence of the hardware platform at the end of partitioning and coding phase in design cycle. In this paper we present the design of easy verification for hardware design. Hardware and software engineer can verify their software program and hardware design for a chip that is emulated in proposed verification environment. Besides, designer can easily design the DEMO system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.13-26
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• 1993

Motion picture algorithms are realized on the multiprocessor system presented in the Study I. For the most efficient processing of the algorithms, pipelining and geometrical parallel processing methods are employed, and processing time, communication load and efficiency of each algorithm are compared. The performance of the implemented system is compared and analysed with reference to MPEG coding algorithm. Theoretical calculations and experimental results both shows that geometrical partitioning is a more suitable parallel processing algorithm for moving picture coding having the advantage of easy algorithm modification and expansion, and the overall efficiency is higher than pipelining.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.106-111
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.