• ETRI Journal
• /
• v.45 no.1
• /
• pp.171-179
• /
• 2023

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13㎛-0.16㎛ to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07b
• /
• pp.1022-1025
• /
• 2002

This paper presents the reliability of planar InP/InGaAs avalanche photodiodes (APD's) with recess etching, which is very crucial for the commercial 10-Gb/s optical receiver application. A versatile design for the planar InP/InGaAs APD's and bias-temperature tests to evaluate long-term reliability at temperature from 200 to $250^{\circ}C$. The reliability is examined by accelerated life tests by monitoring dark current and breakdown voltage. The lifetime of the APD's is estimated by a degradation activation energy. Based on the test results, it is concluded that the planar InP/InGaAs APD's with recess etching shows the sufficient reliability for practical 10-Gb/s optical receivers.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.249-252
• /
• 2002

we have studied the characteristics of PHEMT's with gate recess etching method. The DC characterization of PHTMT fabricated with the wide single recess methods is a maximum drain current density of 319.4 ㎃/mm and a peak transconductance of 336.7 ㎳/mm. The RF measurements were obtained in the frequency range of 1~50GHz. At 50GHz, 3.69dB of 521 gain were obtained and a current gain cut-off frequency(f$_{T}$) of 113 CH and a maximum frequency of oscillation(f$_{max}$) of 172 Ghz were achieved from this device. On the other hand, a maximum drain current of 367 mA/mm, a peak transconduclancc of 504.6 mS/mm, S$_{21}$ gain of 2.94 dB, a current gain cut-off frequency(f$_{T}$) of 101 CH and a maximum frequency of oscillation(f$_{max}$) of 113 fa were achieved from the PHEMT's fabricated by the .narrow single recess methods.methods.

• ETRI Journal
• /
• v.27 no.3
• /
• pp.304-311
• /
• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.05c
• /
• pp.148-152
• /
• 2001

One set of MMIC library has been developed using gate recess etching by spin processor. It is superior than that of dipping Method in the uniformity and the reproducibility of gate recess. A DC characteristics of p-HEMT have a uniform characteristics in the whole wafer than that of dipping method. The low noise p-HEMT with the $0.6{\mu}m$ and $200{\mu}m$ of gate length and gate width, respectivily, has a uniform characteristics of Idss 130~145 mA, conductances 190~220mS/nm, and threshold voltage -0.7~-1.1V in the drain voltage of 2V.

• Journal of IKEEE
• /
• v.13 no.4
• /
• pp.23-27
• /
• 2009

Ohmic contact formation and etching processes for the fabrication of MBE (molecular beam epitaxy) grown GaSb-based p-channel HEMT devices on Si substrate have been studied. Firstly, mesa etching process was established for device isolation, based on both HF-based wet etching and ICP-based dry etching. Ohmic contact process for the source and drain formation was also studied based on Ge/Au/Ni/Au metal stack, which resulted in a contact resistance as low as $0.683\;{\Omega}mm$ with RTA at $320^{\circ}C$ for 60s. Finally, for gate formation of HEMT device, gate recess process was studied based on AZ300 developer and citric acid-based wet etching, in which the latter turned out to have high etching selectivity between GaSb and AlGaSb layers that were used as the cap and the barrier of the device, respectively.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.213-216
• /
• 2002

A double-heterostructure AIGaAs/GaAs PHEMT (Pseudomorphic High Electron Mobility Transistor) using digital recess has been successfully realized. Futhermore, the differences of gm,nax, fT, fmax between two samples are as low as 0.62%, 1.58% and 2.56 % respectively. Experimental results are presented demonstrating the etch rate and Process invariability with respect to hydrogen peroxide and acid exposure times with uniformity among devices on a sample.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.5
• /
• pp.365-370
• /
• 1998

We studied a electrical properties in GaAs/AlGaAs/InGaAs pseudomorphic high electron mobility transistors(PHEMT s) recessed by electron cyclotron resonance(ECR) plasma and wet etching. Using the $NH_4OH$ solution, a nonvolatile AlF$_3$layer formed on AlGaAs surface after selective gate recess is effectively eliminated. Also, we controlled threshold voltage($V_th$) using $H_3PO_4$ etchant. We have fabricated a device with 540 mS/mm maximum transconductance and -0.2 V threshold voltage by using $NH_4OH$ and $H_3PO_4$dip after ECR gate recessing. In a 2-finger GaAs PHEMT with a gate length of 0.2$\mu m$ and width of 100 $\mu m$, a current gain of 15 dB at 10 GHz and a maximum cutoff frequency of 58.9 GHz have been obtained from the measurement of current gain as a function of frequency at 12mA $I_{dss}$ and 2 V souce-drain voltage.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.2
• /
• pp.77-79
• /
• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.1
• /
• pp.31-38
• /
• 2002

In order to improve the 0.35 $mutextrm{m}$-via hole etching process the etching characteristic of the gas $C_2F_{6}$ has been analyzed. The samples were triple-layer films(TEOS/SOG/TEOS) on 8-inch wafers and the orthogonal array matrix technique was used for the process. The equipment for etching was the transformer coupled plasma (TCP) source which is a type of high density plasma(HDP). This experiment showed the etching rate for $C_2F_{6}$ was 0.8 $mutextrm{m}$/min-1.1 $mutextrm{m}$/min and the measured uniformity was under $pm$6.9% in the matrix window. The CD skew comparison between pre and post-etching was under 10% which is an outstanding results in the window of profile in anisotropic etching. There was no problem in C2F6 with the flow rate of 20sccm, but when 14sccm of $C_2F_{6}$ was supplied there was a recess problem on the inner wall of SOG film. Consequently the etching characteristic of $C_2F_{6}$ shows a fast etching rate and a very wide process window in HDP TCP.