• ETRI Journal
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• 제45권1호
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• pp.171-179
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• 2023

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13㎛-0.16㎛ to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.1022-1025
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• 2002

This paper presents the reliability of planar InP/InGaAs avalanche photodiodes (APD's) with recess etching, which is very crucial for the commercial 10-Gb/s optical receiver application. A versatile design for the planar InP/InGaAs APD's and bias-temperature tests to evaluate long-term reliability at temperature from 200 to $250^{\circ}C$. The reliability is examined by accelerated life tests by monitoring dark current and breakdown voltage. The lifetime of the APD's is estimated by a degradation activation energy. Based on the test results, it is concluded that the planar InP/InGaAs APD's with recess etching shows the sufficient reliability for practical 10-Gb/s optical receivers.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.249-252
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• 2002

we have studied the characteristics of PHEMT's with gate recess etching method. The DC characterization of PHTMT fabricated with the wide single recess methods is a maximum drain current density of 319.4 ㎃/mm and a peak transconductance of 336.7 ㎳/mm. The RF measurements were obtained in the frequency range of 1~50GHz. At 50GHz, 3.69dB of 521 gain were obtained and a current gain cut-off frequency(f$_{T}$) of 113 CH and a maximum frequency of oscillation(f$_{max}$) of 172 Ghz were achieved from this device. On the other hand, a maximum drain current of 367 mA/mm, a peak transconduclancc of 504.6 mS/mm, S$_{21}$ gain of 2.94 dB, a current gain cut-off frequency(f$_{T}$) of 101 CH and a maximum frequency of oscillation(f$_{max}$) of 113 fa were achieved from the PHEMT's fabricated by the .narrow single recess methods.methods.

• ETRI Journal
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• 제27권3호
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• pp.304-311
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• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 연구회
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• pp.148-152
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• 2001

One set of MMIC library has been developed using gate recess etching by spin processor. It is superior than that of dipping Method in the uniformity and the reproducibility of gate recess. A DC characteristics of p-HEMT have a uniform characteristics in the whole wafer than that of dipping method. The low noise p-HEMT with the $0.6{\mu}m$ and $200{\mu}m$ of gate length and gate width, respectivily, has a uniform characteristics of Idss 130~145 mA, conductances 190~220mS/nm, and threshold voltage -0.7~-1.1V in the drain voltage of 2V.

• 전기전자학회논문지
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• 제13권4호
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• pp.23-27
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• 2009

실리콘 기판 상에 MBE (molecular beam epitaxy)로 형성된 GaSb 기반 p-channel HEMT 소자를 제작하기 위하여 오믹 접촉 형성 공정과 식각 공정을 연구하였다. 먼저 각 소자의 절연을 위한 메사 식각 공정 연구를 수행하였으며, HF기반의 습식 식각 공정과 ICP(inductively coupled plasma)를 이용한 건식 식각 공정이 모두 사용되었다. 이와 함께 소스/드레인 영역 형성을 위한 오믹 접촉 형성 공정에 관한 연구를 진행하였으며 Ge/Au/Ni/Au 금속층 및 $300^{\circ}C$ 60초 RTA공정을 통해 $0.683\;{\Omega}mm$의 접촉 저항을 얻을 수 있었다. 더불어 HEMT 소자의 게이트 형성을 위한 게이트 리세스 공정을 AZ300 현상액과 citric산 기반의 습식 식각을 이용하여 연구하였으며, citric산의 경우 소자 구조에서 캡으로 사용된 GaSb와 베리어로 사용된 AlGaSb사이에서 높은 식각 선택비를 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.213-216
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• 2002

A double-heterostructure AIGaAs/GaAs PHEMT (Pseudomorphic High Electron Mobility Transistor) using digital recess has been successfully realized. Futhermore, the differences of gm,nax, fT, fmax between two samples are as low as 0.62%, 1.58% and 2.56 % respectively. Experimental results are presented demonstrating the etch rate and Process invariability with respect to hydrogen peroxide and acid exposure times with uniformity among devices on a sample.

• 한국전기전자재료학회논문지
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• 제11권5호
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• pp.365-370
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• 1998

We studied a electrical properties in GaAs/AlGaAs/InGaAs pseudomorphic high electron mobility transistors(PHEMT s) recessed by electron cyclotron resonance(ECR) plasma and wet etching. Using the $NH_4OH$ solution, a nonvolatile AlF$_3$layer formed on AlGaAs surface after selective gate recess is effectively eliminated. Also, we controlled threshold voltage($V_th$) using $H_3PO_4$ etchant. We have fabricated a device with 540 mS/mm maximum transconductance and -0.2 V threshold voltage by using $NH_4OH$ and $H_3PO_4$dip after ECR gate recessing. In a 2-finger GaAs PHEMT with a gate length of 0.2$\mu m$ and width of 100 $\mu m$, a current gain of 15 dB at 10 GHz and a maximum cutoff frequency of 58.9 GHz have been obtained from the measurement of current gain as a function of frequency at 12mA $I_{dss}$ and 2 V souce-drain voltage.

• 전자공학회논문지A
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• 제29A권2호
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• 대한전자공학회논문지SD
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• 제39권1호
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• pp.31-38
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• 2002

0.35㎛-비아(via) 식각공정을 개선하기 위하여 C₂F/sub 6/가스의 식각특성을 분석하였다. 실험한 재료는 TEOS/SOG/TEOS 막을 올린 8인치 웨이퍼이며, 실험의 기법은 직교행열(Orthogonal array matrix) 실험 방식을 활용하였다. 산화막 식각에 이용된 장비는 transformer coupled plasma(TCP) source 방식이며 고밀도 플라즈마(HDP)장비이다. 실험의 결과는, 실험변수의 범위 내에서 C₂F/sub 6/는 0.8㎛/min-1.l㎛/min 범위의 식각속도를 보이며 균일도(Uniformity)는 ±6.9%미만으로 측정되었다. CD 변화(skew)는 식각 전과 후를 비교하여 10% 미만이었고 그 결과 비등방성(anisotropic) 식각의 특성이 우수하였다. C₂F/sub 6/를.20sccm 공급할 때 문제점이 발견되지 않았지만 14sccm을 공급하면 SOG 막의 내벽이 침식당하는 문제점이 있었다. 결과적으로 C₂F/sub 6/는 HDP TCP에서 빠른 식각비와 넓은 공정창(process window)을 가진 식각특성을 나타내었다.