• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.9
• /
• pp.115-124
• /
• 2004

This paper proposes a high efficient and low power FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels; it is a 6-bit, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of 4 pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter is actually implemented and the chip dissipates 120mV at 100MHz, uses a 3.3V power supply and occupies 1.88 ${\times}$ 1.38 $\textrm{mm}^2$. The implemented filter requires approximately 11.7% less power compared with the existing architectures that use the similar technology.

• ETRI Journal
• /
• v.37 no.5
• /
• pp.906-916
• /
• 2015

High-speed I/O channels require adaptive techniques to optimize the settings for filter tap weights at decision feedback equalization (DFE) read channels to compensate for channel inter-symbol interference (ISI) and crosstalk from multiple adjacent channels. Both ISI and crosstalk tend to vary with channel length, process, and temperature variations. Individually optimizing parameters such as those just mentioned leads to suboptimal solutions. We propose a joint optimization technique for crosstalk cancellation (XTC) at DFE to compensate for both ISI and XTC in high-speed I/O channels. The technique is used to compensate for between 15.7 dB and 19.7 dB of channel loss combined with a variety of crosstalk strengths from $60mV_{p-p}$ to $180mV_{p-p}$ adaptively, where the transmit non-return-to-zero signal amplitude is a constant $500mV_{p-p}$.

• Proceedings of the IEEK Conference
• /
• 2000.09a
• /
• pp.255-258
• /
• 2000

본 논문에서는 효율적인 면적의 저전력 FIR 필터를 제안한다. 제안된 필터는 6 비트 8 탭의 구조를 갖는PRML(Partial-Response Maximum Likelihood) 디스크드라이브 read channel용 FIR 필터이다 제안된 구조는 병렬연산 구조를 채택하고 있으며 네 단의 파이프라인 구조를 가지고 있다. 곱셈을 위하여 부스 알고리즘이 사용되며 압축기를 이용하여 덧셈을 수행한다. 저전력을 위해 CMOS 패스 트랜지스터를 사용하였으며 면적을 줄이기 위해 single-rail 로직을 사용하였다 제안된 구조를 0.65㎛ CMOS 공정을 이용하여 설계하였으며1.88 × 1.38㎟의 면적을 차지하였고 HSPICE 시뮬레이션 결과 3.3V의 공급전압에서 100㎒로 동작시 120㎽의 전력을 소모한다. 제안된 구조는 기존의 구조들에 비해 약 11%의 전력이 감소했으며 약 33%의 면적이 감소하였다.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.775-778
• /
• 1998

근래에 들어 컴퓨터 기술은 멀티미디어 기수의 발달과 더불어 그에 따른 데이터량의 증가로 인해 데이터를 처리, 전송, 저장하는 모든 부문에서의 고속, 대용량화를 요구하고 있다. 이 중에서 특히 저장장치 부문은 응용 프로그램이 대형화되고 멀티미디어화에 따른 데이터량이 크게 증가하는 추세에 있기 때문에 지속적인 용량 증가가 요구되고 있다. 이런 상황에서 주목을 받고 있는 것이 신호처리 방식을 개선하여 저장장치의 기록 밀도를 향상시키는 기술의 하나인 partial response maximum likelihood (PRML) 기술이다. PRML 방식은 HDD 나 광 디스크로부터 데이터를 읽어낼때의 신호처리 기술 중의 ㅎ나로 신호간 간섭을 허용하여 데이터 속도를 증가시키고, 신호를 재생할 때 신호간 간섭을 보상하여 원래 신호를 복원해 내는 기술이다. 이를 이용하면 기존의 기록방식에 비해 기록밀도를 20-50% 정도 높일 수 있다.〔1〕〔2〕

• Journal of electromagnetic engineering and science
• /
• v.1 no.2
• /
• pp.131-138
• /
• 2001

The DTV (Digital TV) tuner for an 8-VSB (Vestigial Side-Band) modulation was developed to meet the requirements of the ATSC (Advanced Television Systems Committee). The double frequency conversion and the active tracking filter in the front-end were used to cancel interferences between adjacent channels and multi-channels by suppressing the IF beat and the Image frequency. However, It was impossible to get frequency mapping between the tracking filter and the first VCO (Voltage Controlled Oscillator) in the existing DTV tuner structure which differs from the NTSC (National Television Systems Committee) tuner. This paper, therefore, suggests an assailable structure and a new method for the automatic frequency selection by mapping the frequency characteristics over the tracking voltage and the combined HW which is composed of a Micro-controller, an EEPROM (Electrically Erasable Programmable Read Only Memory), a DAC (Digital-to-Analog Converter), an OP amplifier, and a switch driver.

• International Journal of Advanced Culture Technology
• /
• v.7 no.4
• /
• pp.236-241
• /
• 2019

This paper will read about a multichannel frequency-modulated continuous wave (FMCW) radar sensor with switching transmit (TX) antennas is developed at W-band. To achieve a high angular resolution, a uniform linear array consisting of 5 switching-TX and 12 receive (RX) antennas is employed with the digital beamforming technique. The overall radar front-end module comprises a W-band transceiver and TX/RX antennas. A multichannel transceiver module consists of 5 up-conversion and 12 down-conversion channels, where one of the TX channels is sequentially switched ON. For developing transmitter, we developed an HPA (high power amplified) MMIC chip for W-band radar system and fabricated a transmitter module using this chip. In order to develop the W-band transmitter, we analyzed the important antenna transition structure from HPA MMIC line to W/G (Waveguide)antenna via M/S(microstrip) and fabricated it with 5 transmission channels. As a result, the output power of the transmitter was within 1 dB of the error range after analysis and measurement under normal temperature and environmental conditions.

• Journal of the Korea Society of Computer and Information
• /
• v.18 no.2
• /
• pp.69-76
• /
• 2013

Reader-to-reader interference in RFID system is occurred due to the use of limited number of frequencies, and this is the main cause of read rate reduction in the passive RFID tags. Therefore, in order to maximize the read rate under the circumstances of limited frequency resources, it is necessary to minimize the frequency interference among RFID readers. This paper presents a hybrid FDM/TDM constraint satisfaction problem models for frequency interference minimization problems of the RFID readers, and assigns optimal channels to each readers using conventional backtracking search algorithms. A depth first search based on backtracking are accomplished to find solutions of constraint satisfaction problems. At this moment, a variable ordering algorithm is very important to find a solution quickly. Variable ordering algorithms applied in the experiment are known as efficient in the graph coloring. To justify the performance of the proposed constraint satisfaction problem model, optimal channels for each readers in the passive UHF RFID system are allocated by using computer simulation satisfying various interference constraints.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.780-783
• /
• 2012

Recently, the SoC industry mainly uses various multi-layered bus architectures. However, reckless use of bus layers may results in on-chip communication resources and waste of silicon area. This paper performs a quantitative analysis to compare the two de-facto on-chip buses and SNP. Through the performance estimation, the performance of SNP turns out to be significantly enhanced for asymmetric write and read traffic (non-central F distribution) while symmetric traffic is similar to that of AXI. More specifically, SNP properly places IP cores on the top or bottom, induces the write and read channels to be balanced, and achieves about twenty percent improved performance compared to AXI.

• Parasites, Hosts and Diseases
• /
• v.54 no.6
• /
• pp.751-758
• /
• 2016

This study aimed at constructing a draft genome of the adult female worm Toxocara canis using next-generation sequencing (NGS) and de novo assembly, as well as to find new genes after annotation using functional genomics tools. Using an NGS machine, we produced DNA read data of T. canis. The de novo assembly of the read data was performed using SOAPdenovo. RNA read data were assembled using Trinity. Structural annotation, homology search, functional annotation, classification of protein domains, and KEGG pathway analysis were carried out. Besides them, recently developed tools such as MAKER, PASA, Evidence Modeler, and Blast2GO were used. The scaffold DNA was obtained, the N50 was 108,950 bp, and the overall length was 341,776,187 bp. The N50 of the transcriptome was 940 bp, and its length was 53,046,952 bp. The GC content of the entire genome was 39.3%. The total number of genes was 20,178, and the total number of protein sequences was 22,358. Of the 22,358 protein sequences, 4,992 were newly observed in T. canis. Following proteins previously unknown were found: E3 ubiquitin-protein ligase cbl-b and antigen T-cell receptor, zeta chain for T-cell and B-cell regulation; endoprotease bli-4 for cuticle metabolism; mucin 12Ea and polymorphic mucin variant C6/1/40r2.1 for mucin production; tropomodulin-family protein and ryanodine receptor calcium release channels for muscle movement. We were able to find new hypothetical polypeptides sequences unique to T. canis, and the findings of this study are capable of serving as a basis for extending our biological understanding of T. canis.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.5
• /
• pp.241-249
• /
• 2015

Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.