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Highly Efficient and Low Power FIR Filter Chip for PRML Read Channel  

Jin Yong, Kang (Samsung Electro-Mechanics)
Byung Gak, Jo (Agency for Defense Development)
Myung Hoon, Sunwoo (Electrical and Computer Engineering, Ajou Univ)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.9, 2004 , pp. 115-124 More about this Journal
Abstract
This paper proposes a high efficient and low power FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels; it is a 6-bit, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of 4 pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter is actually implemented and the chip dissipates 120mV at 100MHz, uses a 3.3V power supply and occupies 1.88 ${\times}$ 1.38 $\textrm{mm}^2$. The implemented filter requires approximately 11.7% less power compared with the existing architectures that use the similar technology.
Keywords
FIR filter; CMOS pass-transistor; PRML; read channels; disk drives.;
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