• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.233-238
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• 2016

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.1-11
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• 2012

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.219-224
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• 2015

Recently, the multi-core processor architecture is widely used in the digital signal processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multi-core processors are known to have higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core digital signal processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric quad-core, octa-core and hexadeca-core digital signal processors and compared with the symmetric ones of similar hardware budget using UTDSP benchmarks as input.

• Journal of IKEEE
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• v.17 no.4
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• pp.564-569
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• 2013

The current embedded devices are growing rapidly in the multi-core, and these demand fast boot time. But method of previous boot uses core only one. The method includes parallel techniques and modification of CPU Frequency policy. Parallel methods, after analyzing the Android boot process with analysis tool, applied to location where a lot of CPU operation. CPU Frequency policy is modified for high performance of core. The proposed method was applied to S5PV310 dual core and Exynos4412 quad core embedded system. As a result of the experiment, we found that the proposed method makes boot time fast about 20.71% and 31.34% in dual core and quad core environment as compared with the previous method.

• The KIPS Transactions:PartB
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• v.18B no.4
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• pp.173-180
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• 2011

This paper shows an approach for real-time object segmentation on GPU (Graphics Processing Unit) using CUDA (Compute Unified Device Architecture). Recently, many applications that is monitoring system, motion analysis, object tracking or etc require real-time processing. It is not suitable for object segmentation to procedure real-time in CPU. NVIDIA provide CUDA platform for Parallel Processing for General Computation to upgrade limit of Hardware Graphic. In this paper, we use adaptive Gaussian Mixture Background Modeling in the step of object extraction and CCL(Connected Component Labeling) for classification. The speed of GPU and CPU is compared and evaluated with implementation in Core2 Quad processor with 2.4GHz.The GPU version achieved a speedup of 3x-4x over the CPU version.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1349-1354
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• 2014

This paper presents a compact and portable high-voltage generator based on magnetic-core Tesla transformer for driving an UWB high power electromagnetic source. In order to optimize the performance of the high-voltage generator, a novel open-loop cylindrical magnetic-core adopting the quad-division lamination structure is proposed and manufactured. The designed high-voltage generator using the proposed magnetic core has a battery-powered operation and compact size of $280mm{\times}150mm$ in length and diameter, respectively. The high-voltage generator can produce a voltage pulse waveform with peak amplitude of 450 kV, a rise time of 1.5 ns, and pulse duration of 2.5 ns at the 800 V input voltage.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.2
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• pp.55-62
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• 2009

The power consumption of a high-end microprocessor increases very rapidly. High power consumption will lead to a rapid increase in the chip temperature as well. If the temperature reaches beyond a certain level, chip operation becomes either slow or unreliable. Therefore various approaches for Dynamic Thermal Management (DTM) have been proposed. In this paper, we propose a learning based temperature prediction scheme for a multi-core system. In this approach, from repeatedly executing an application, we learn the thermal patterns of the chip, and we control the temperature in advance through DTM. When the predicted temperature may go beyond a threshold value, we reduce the temperature by decreasing the operation frequencies of the corresponding core. We implement our temperature prediction on an Intel's Quad-Core system which has integrated digital thermal sensors. A Dynamic Frequency System (DFS) technique is implemented to have four frequency steps on a Linux kernel. We carried out experiments using Phoronix Test Suite benchmarks for Linux. The peak temperature has been reduced by on average $5^{\circ}C{\sim}7^{\circ}C$. The overall average temperature reduced from $72^{\circ}C$ to $65^{\circ}C$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.163-169
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• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

• Journal of Digital Convergence
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• v.13 no.12
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• pp.381-390
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• 2015

One of the fundamental requirements of entertainment applications is interactivity with users. The mobile device such as the smartphone, however, does not guarantee it due to the limit of the application processor's computing power, memory size and available electric power of the battery. This paper proposes a methodology to boost responsiveness of interactive applications by taking advantage of the parallel architecture of mobile devices which, for instance, have dual-core, quad-core or octa-core. To harness the multi-core architecture, it exploits the POSIX thread, a platform-independent thread library to be able to be used in various mobile platforms such as Android, iOS, etc. As a useful application example of the methodology, a heavy matrix calculation function was transformed to a parallelized version which showed around 2.5 ~ 3 times faster than the original version in a real-world usage environment.

• Journal of the Korean Institute of Educational Facilities
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• v.19 no.6
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• pp.3-14
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• 2012

University campus has grown and developed along with history of human in connection with transition characteristics of city. In particular, reflecting the features in the times, the masterplan should explore its main roles today when international growth of university is pursued. In particular, center core and quad space, focusing on main components of campus such as main building, student union hall and main lecture facility, are the prototype of campus components and have been pursued to have importance in terms of shape and function as traditional campus space strategy. Recently, however, new strategy has been proposed to explore orders of campus utilizing the underground space focusing on main universities. Design of Hana Plaza of Korea University and Bekyangro of Yeonsei University, the targets of this study, actively explore this strategy. This study analyzed such strategies in terms of concept of space to obtain space, design trend of main universities at home and abroad, and viewpoint of integrated masterplan proposal. Conclusions from this study are as follows. First, concept of quad and center space found in the design of traditional campus is reinterpreted into new design aspects through development of underground space. Second, development of underground space is approached to overcome the limit of existing campus and to present the vision of universities 100 years ahead. Third, ever-changing complicated urban environment has been reflected in space configuration of campus and positioned as strategy to implement this as modern construction technique. Third, implementation of pedestrian-oriented campus has been pursued by reinforcing utilization of inclined topography of urban environment in Korea. This enables to obtain spaces for main activities of students and to implement the space where student support facilities are concentrated and activities are performed actively. Such features can be presented as conclusions of this study.