• Title/Summary/Keyword: pulse-width control

Search Result 805, Processing Time 0.03 seconds

New hysteresis current control for induction motor drive with NPC inverter (NPC 인버터에 의한 유도전동기 구동시스템의 새로운 히스테리시스 전류 제어기법)

  • 김춘삼;이병송
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.13 no.1
    • /
    • pp.46-52
    • /
    • 1999
  • A new current controlled PWM t'||'&'||'pound;rlmique with NPC(Neutral Point Qarll)ed) structure is IrOIX>Sed in this paper. A current controlled PWM technique with neutral-JXlint-cIamped pulse-width modulation inverter composed of main switching devices which operates as switch for PWM and auxiliary switching devices to clamp the output terminal potential to the neutral point potential is described. The proposed current controller has a first and second current band The switching pattern will be made by the first current band. According to the second current band, the output state of the switching pattern is changed into positivee and negative state. This inverter output contains less hanronic content and lower switching frequency than that of conventional current controlled PWM technique at the same current limit. Thbe induction machine drive with proposed technique is investigated by commputer simulation.

  • PDF

Digitally Controlled Single-inductor Multiple-output Synchronous DC-DC Boost Converter with Smooth Loop Handover Using 55 nm Process

  • Hayder, Abbas Syed;Park, Young-Jun;Kim, SangYun;Pu, Young-Gun;Yoo, Sang-Sun;Yang, Youngoo;Lee, Minjae;Hwang, Keum Choel;Lee, Kang-Yoon
    • Journal of Power Electronics
    • /
    • v.17 no.3
    • /
    • pp.821-834
    • /
    • 2017
  • This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

The design of the high efficiency DC-DC Converter with Dynamic Threshold MOS switch (Dynamic Threshold MOS 스위치를 사용한 고효율 DC-DC Converter 설계)

  • Ha, Ka-San;Koo, Yong-Seo;Son, Jung-Man;Kwon, Jong-Ki;Jung, Jun-Mo
    • Journal of IKEEE
    • /
    • v.12 no.3
    • /
    • pp.176-183
    • /
    • 2008
  • The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit as a block. The Saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 95% at 100mA output current. And DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

  • PDF

INVESTIGATION OF RUNNING BEHAVIORS OF AN LPG SI ENGINE WITH OXYGEN-ENRICHED AIR DURING START/WARM-UP AND HOT IDLING

  • Xiao, G.;Qiao, X.;Li, G.;Huang, Z.;Li, L.
    • International Journal of Automotive Technology
    • /
    • v.8 no.4
    • /
    • pp.437-444
    • /
    • 2007
  • This paper experimentally investigates the effects of oxygen-enriched air (OEA) on the running behaviors of an LPG SI engine during both start/warm-up (SW) and hot idling (HI) stages. The experiments were performed on an air-cooled, single-cylinder, 4-stroke, LPG SI engine with an electronic fuel injection system and an electrically-heated oxygen sensor. OEA containing 23% and 25% oxygen (by volume) was supplied for the experiments. The throttle position was fixed at that of idle condition. A fueling strategy was used as following: the fuel injection pulse width (FIPW) in the first cycle of injection was set 5.05 ms, and 2.6 ms in the subsequent cycles till the achieving of closed-loop control. In closed-loop mode, the FIPW was adjusted by the ECU in terms of the oxygen sensor feedback. Instantaneous engine speed, cylinder pressure, engine-out time-resolved HC, CO and NOx emissions and excess air coefficient (EAC) were measured and compared to the intake air baseline (ambient air, 21% oxygen). The results show that during SW stage, with the increase in the oxygen concentration in the intake air, the EAC of the mixture is much closer to the stoichiometric one and more oxygen is made available for oxidation, which results in evidently-improved combustion. The ignition in the first firing cycle starts earlier and peak pressure and maximum heat release rate both notably increase. The maximum engine speed is elevated and HC and CO emissions are reduced considerably. The percent reductions in HC emissions are about 48% and 68% in CO emissions about 52% and 78%; with 23% and 25% OEA, respectively, compared to ambient air. During HI stage, with OEA, the fuel amount per cycle increases due to closed-loop control, the engine speed rises, and speed stability is improved. The HC emissions notably decrease: about 60% and 80% with 23% and 25% OEA, respectively, compared to ambient air. The CO emissions remain at the same low level as with ambient air. During both SW and HI stages, intake air oxygen enrichment causes the delay of spark timing and the increased NOx emissions.

ETS Sampler design for borehole radar receiver using 4 different clock phases (위상이 다른 4개의 클럭을 이용한 시추공 레이다 수신기용 ETS 샘플러 설계)

  • Yoo, Young-jae;Oh, Chaegon
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.19 no.1
    • /
    • pp.680-687
    • /
    • 2018
  • Borehole radar is a radar used for underground resources and geological exploration purposes. It needs a high-speed sampler to transmit electromagnetic waves with a pulse width of several ns and to receive reflected waves of several tens to several hundreds of MHz reflected from the object to be surveyed. ETS (Equivalent-Time Sampling), which can achieve sampling performance of several GHz with a sampling frequency of several tens of MHz, is suitable for use as a sampler of a borehole radar receiver. In this paper, we propose a method to control the sampling clock delay, which is the most important factor in ETS sampler design, using four clocks with phase difference of $90^{\circ}$ for one clock source. The proposed method can reduce the time required to acquire the data within the set interval by 1/25 than the conventional method using the delay generator. When the implemented sampler is applied to the receiver of existing borehole radar, it is possible to accumulate 58 additional times due to the shortened sampling time. In addition, by using one delay control logic compared with the conventional method using several sampling clock delay control logic in order to satisfy the target sampling range, it is possible to omit the correction process which was necessary in the past. As a result, the structure of the system can be simplified and a uniform sampler can be realized.

Design of a CCM/DCM dual mode DC-DC Buck Converter with Capacitor Multiplier (커패시터 멀티플라이어를 갖는 CCM/DCM 이중모드 DC-DC 벅 컨버터의 설계)

  • Choi, Jin-Woong;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.17 no.9
    • /
    • pp.21-26
    • /
    • 2016
  • This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

Design of a PWM DC-DC Boost Converter IC for Mobile Phone Flash (휴대전화 플래시를 위한 PWM 전류모드 DC-DC converter 설계)

  • Jung, Jin-Woo;Heo, Yun-Seok;Park, Yong-Su;Kim, Nam-Tae;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.12 no.6
    • /
    • pp.2747-2753
    • /
    • 2011
  • In this paper, a PWM current-mode DC-DC boost converter for mobile phone flash application has been proposed. The converter which is operated with 5 Mhz high switching frequency is capable of reducing mounting area of passive devices such as inductor and capacitor, consequently is suitable for compact mobile phones. This boost converter consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. Meanwhile, the control block consists of pulse width modulator, error amplifier, oscillator etc. Proposed boost converter has been designed and verified in a $0.5\;{\mu}m$ 1-poly 2-metal CMOS process technology. Simulation results show that the output voltage is 4.26 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 Khz driven converter when the duty ratio is 0.15.

A Study and Design of Beam Scanning Array Antenna using IR-UWB (IR-UWB를 이용한 빔 스캐닝 배열 안테나 설계 및 연구)

  • Kim, Keun-Yong;Kang, Eun-Kyun;Kim, Jin-Woo;Ra, Keuk-Whan
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.51 no.3
    • /
    • pp.194-201
    • /
    • 2014
  • This paper is able to be solved by improving degradation in multi-path environment by adjust beam pattern angle through modifying pulse phase of each antennas by using TRM (Transmitter Receiver Module). Beam Scanning Array Antenna, which is transmitter/receiver that improves degradation in multi-path environment without any signal distortion, is designed and manufactured. Beam Scanning Array Antenna should be able to send/receive signal at the antenna's longitudinal part without distortion and should not influences other systems. Also, it should include target detecting ability by beam steering.Dispersion characteristic of Beam Scanning Antenna, which is designed, is analysed by using fidelity, and steering and radar resolution performance is verified by using $1cm{\times}1cm$ sized target. To manufacture Beam Scanning Array Antenna, control board and GUI, which is able to control Vivaldi Antenna for IR-UWB, Tri-Band Wilkinson power divider, and TRM (Transmitter Receiver Module), is designed. Throughout this research, developed Beam Scanning UWB Array Antenna system is adoptable for radar application field. and time domain analysis techniques by using network analyser made the antenna characteristics analysis for setting up antenna more accurate. In addition, it makes beam width checking without difficulties.

A Low Area and High Efficiency SMPS with a PWM Generator Based on a Pseudo Relaxation-Oscillating Technique (Pseudo Relaxation-Oscillating 기법의 PWM 발생기를 이용한 저면적, 고효율 SMPS)

  • Lim, Ji-Hoon;Wee, Jae-Kyung;Song, Inchae
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.50 no.11
    • /
    • pp.70-77
    • /
    • 2013
  • We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

The Characteristics Analysis and Design of High-Frequency Isolated Type ZVZCS PS-PWM DC-DC Converter with Fuel Cell Generation System (연료전지 발전시스템에 적용된 고주파 절연형 ZVZCS PS-PWM DC-DC 컨버터의 설계 및 특성 해석)

  • Suh, Ki-Young;Mun, Sang-Pil;Kim, Dong-Hun;Lee, Hyun-Woo;Kwon, Soon-Kurl
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.20 no.4
    • /
    • pp.21-28
    • /
    • 2006
  • In this paper, the proposed full-bridge high frequency isolated zoo voltage and zero current switching phase shifted pulse width modulation(ZVZCS PS-PWM)DC-DC converter among fuel cell generation system consist of 1.2[kW] fuel cell of Nexa Power Module, full-bridge DC-DC converter to boost the fuel cell low voltage($28{\sim}43[%]$) to 380[VDC] and a single phase full-bridge inverter is implemented to produce AC output(220[VAC], 60[Hz]). A tapped inductor filter with freewheeling diode is newly implemented in the output filter of the proposed full-bridge high frequency isolated ZVZCS PS-PWM DC-DC converter to suppress circulating current under the wide output voltage regulation range, thus to eliminate the switching and transformer turn-on/off over-short voltage or transient phenomena. Besides the efficiency of $93{\sim}97[%]$ is obtained over the wide output voltage regulation ranges and load variations.