• Journal of Power Electronics
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• v.18 no.4
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• pp.1027-1036
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• 2018

In this paper a new generalized space vector pulse width modulation scheme is proposed based on the principle of reverse mapping to drive the switches of multilevel inverters. This projected scheme is developed based on the middle vector of the subhexagon which holds the tip of the reference vector, which plays a major role in mapping the reference vector. A new approach is offered to produce middle vector of the subhexagon which holds tip of the reference vector in the multilevel space vector plane. By using middle vector of the subhexagon, reference vector is linked towards the inner two level sub-hexagon. Then switching vectors, switching sequence and dwell times corresponding to a particular sector of a two-level inverter are determined. After that, by using the two level stage findings, the switching vectors related to exact position of the reference vector are directly generated based on principle of the reverse mapping approach and do not need to be found at n level stage. In the reverse mapping principle, the middle vector of subhexagon is added to the formerly found two level switching vectors. The proposed generalized algorithm is efficient and it can be applied to an inverter of any level. In this paper, the proposed scheme is explained for a five-level inverter and the performance is analyzed for five level and three level inverters through MATLAB. The simulation results are validated by implementing the propose scheme on a V/f controlled three-level inverter fed induction motor using dSPACE control desk.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1540-1551
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• 2015

The detection of position and speed in BLDC motors without using position sensors has meant many efforts for the last decades. The aim of this paper is to develop a sensorless technique for detecting the position and speed of BLDC motors, and to overcome the drawbacks of position sensor-based methods by improving the performance of traditional approaches oriented to motor phase voltage sensing. The position and speed information is obtained by computing the derivative of the terminal phase voltages regarding to a virtual neutral point. For starting-up the motor and implementing the algorithms of the detection technique, a FPGA board with a real-time processor is used. Also, a versatile hardware has been developed for driving BLDC motors through pulse width modulation (PWM) signals. Delta and wye winding motors have been considered for evaluating the performance of the designed hardware and software, and tests with and without load are performed. Experimental results for validating the detection technique were attained in the range 5-1500 rpm and 5-150 rpm under no-load and full-load conditions, respectively. Specifically, speed and position square errors lower than 3 rpm and between 10º-30º were obtained without load. In addition, the speed and position errors after full-load tests were around 1 rpm and between 10º-15º, respectively. These results provide the evidence that the developed technique allows to detect the position and speed of BLDC motors with low accuracy errors at starting-up and over a wide speed range, and reduce the influence of noise in position sensing, which suggest that it can be satisfactorily used as a reliable alternative to position sensors in precision applications.

• Journal of Korean Neurosurgical Society
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• v.37 no.2
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• pp.112-115
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• 2005

Objective: Thalamic lesioning and deep brain stimulation(DBS) have proved to be beneficial to the treatment of essential tremor(ET). The authors compared the effects and complications of two modalities. Methods: A total of 34 patients with ET were treated with ventral intermediate(Vim) nucleus thalamotomy or Vim DBS from May 1999 to May 2003. The procedure of lesioning or stimulation were performed as usual manner with or without microelectrode recording. Postoperatively, utilizing the various combinations of frequency, voltage and pulse width optimized the stimulation. The degree of improvements of tremor and the occurrence of the complications were evaluated postoperatively and at follow-up. Results: There were 38 procedures, including 27 with Vim thalamotomy and 11 with DBS, in 34 patients. Of the thalamotomy group, left Vim lesioning is 25 and right one is 2. Follow-up duration ranged from 12 to 57 months. In the thalamotomy group, the rate of overall good outcome was 88.9% but 12 patients (44.4%) showed permanent adverse effects. In the cases of stimulation, the rate of overall good outcome was 90.9% and two patients had acceptable dysarthria. Conclusion: Both Vim thalamotomy and Vim DBS were effective for the treatment of ET, although perioperative adverse effects tended to be higher in patients who had thalamotomy. In cases of DBS, adjustments of stimulation parameters enabled an acceptable position to be achieved with tremor control and unwanted effects.

• The Journal of Korean Physical Therapy
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• v.22 no.1
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• pp.67-73
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• 2010

Purpose: We tested whether repetitive transcranial magnetic stimulation (rTMS) improved recovery following spinal cord injury (SCI) in rats with transplantation of adipose tissue-derived stromal cells (ATSCs). Methods: Twenty Sprague-Dawley rats (200-250 g, female) were used. Moderate spinal cord injury was induced at the T9 level by a New York University (NYU) impactor. The rat ATSCs (approximately $5{\times}10^5$ cells) were injected into the perilesional area at 9 days after SCI. Starting four days after transplantation, rTMS (25 Hz, 0.1 Tesla, pulse width=$370{\mu}s$, on/off time=3 sec/3 sec) was applied daily for 7 weeks. Functional recovery was assessed using the Basso, Beattie, and Bresnahan (BBB) locomotor rating scale as well as pain responses for thermal and cold stimuli. Results: Both groups showed similar, gradual improvement of locomotor function. rTMS stimulation decreased thermal and cold hyperalgesia after 7 weeks, but sham stimulation did not. Conclusion: rTMS after transplantation of ATSCs in an SCI model may reduce thermal hyperalgesia and cold allodynia, and may be an adjuvant therapeutic tool for pain control after stem cell therapy in SCI.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1239-1247
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• 2012

In this paper, design and fabrication of solid state power amplifier(SSPA) using GaN HEMT chip for X-band frequency are presented. The SSPA consists of the power supply for stable power and the control unit for communication and controlling the internal module, the RF Part to amplify RF signal, In particular the adopted active device for the RF Parts is GaN HEMT Bare chip of TriQuint company, the RF parts consists of pre-stage, drive-stage, main power-stage and each amplifier is designed with input and out matching circuit. The developed power amplifier demonstrated more than 300 W peak output power in condition of 26 % duty, max. pulse width 100us for the X-band frequency( 500 MHz bandwidth) and can apply to marine radar systems.

• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• Journal of the Semiconductor & Display Technology
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• v.12 no.2
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• pp.13-17
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• 2013

In lighting system where several large-area organic light-emitting diode (OLED) lighting panels are involved, panel aging may appear differently from each other, resulting in a falling-off in lighting quality. To achieve uniform light output across large-area OLED lighting panels, we have employed an optical feedback circuit. Light output from each OLED panel is monitored by the optical feedback circuit that consists of a photodiode, I-V converter, 10-bit analogdigital converter (ADC), and comparator. A photodiode generates current by detecting OLED light from one side of the glass substrate (i.e., edge emission). Namely, the target luminance from the emission area (bottom emission) of OLED panels is monitored by current generated from the photodiode mounted on a glass edge. To this end, we need to establish a mapping table between the ADC value and the luminance of bottom emission. The reference ADC value corresponds to the target luminance of OLED panels. If the ADC value is lower or higher than the reference one (i.e., when the luminance of OLED panel is lower or higher than its target luminance), a micro controller unit (MCU) adjusts the pulse width modulation (PWM) used for the control of the power supplied to OLED panels in such a way that the ADC value obtained from optical feedback is the same as the reference one. As such, the target luminance of each individual OLED panel is unchanged. With the optical feedback circuit included in the lighting system, we have observed only 2% difference in relative intensity of neighboring OLED panels.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.11a
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• pp.387-390
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• 2005

A This paper presents a novel three-phase current-fed Pulse Width Modulation converter with switched- capacitor type resonant DC link commutation circuit operating PWM pattern strategy under a design consideration of low-pass filter, which can operate on the basis of the principle of zero current soft-switching commutation. In the first place, the steady-state operating principle of this converter with a new resonant DC link snubber circuit is described in connection with the equivalent operation circuit, together with the practical design procedure of the switched-capacitor type resonant DC link circuit is discussed from a theoretical viewpoint on the basis of a design example for high-power applications. The actively delayed time correction method to compensate distorted currents due to a relatively long resonant commutation time is newly implemented in the open loop control scheme so as to acquire the new optimum PWM pattern. Finally, the experiment or set-up in laboratory system or this converter is concretely demonstrated herein to confirm a zero current soft-switching commutation of this converter. The comparative evaluations between current-fed hard switching PWM and soft-switching PWM converters are carried out from a viewpoint of their PWM converter characteristics.