• ETRI Journal
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• 제27권6호
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• pp.651-665
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• 2005

This paper proposes a generic security architecture designed for a multidomain and multiservice network based on programmable networks. The multiservice network allows users of an IP network to run programmable services using programmable nodes located in the architecture of the network. The programmable nodes execute codes to process active packets, which can carry user data and control information. The multiservice network model defined here considers the more pragmatic trends in programmable networks. In this scenario, new security risks that do not appear in traditional IP networks become visible. These new risks are as a result of the execution of code in the programmable nodes and the processing of the active packets. The proposed security architecture is based on symmetric cryptography in the critical process, combined with an efficient manner of distributing the symmetric keys. Another important contribution has been to scale the security architecture to a multidomain scenario in a single and efficient way.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.279-282
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• 1999

Frequency divider selects the channel of the frequency synthesizer. General programmable divider has many flip-flops to realize all integer division value and stability problem by using dual modules prescaler. In this paper, a new architecture of programmable divider is proposed and designed to improve these problems. The proposed programmable divider has only thirteen flip-flops. The programmable divider is designed by 0.65${\mu}{\textrm}{m}$ CMOS technology and HSPICE. Operating frequency of the programmable divider is 200MHz with a 3V supply voltage.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.926-931
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• 2004

In this paper, we proposed security management architecture that combines programmable network technology and policy based network management technology to manage efficiently heterogeneous security systems. By using proposed security management architecture, a security administrator can manage heterogeneous security systems using security policy, which is automatically translated into a programmable security policy and executed on programmable middleware of security system. In addition, programmable middleware that has the features of programmable network can reduce excessive management traffic. We showed that the programmable middleware could reduce the load of management traffic by comparing processing time between the proposed architecture and PBNM architecture.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.419-421
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• 1987

The high-speed tendency of Programmable Controller requires a fast processing of instruction. This project investigate the instruction execution system for a fast processing in Programmable Controller.

• 한국통신학회논문지
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• 제28권10C호
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• pp.1033-1044
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• 2003

본 논문에서는 이기종의 보안 장비를 보다 효율적으로 관리할 수 있는 보안 관리 구조와 관리 트래픽의 부하를 줄일 수 있는 프로그래머블 미들웨어를 제안하였다. 제안된 보안 관리 구조는 정책 기반 네트워크 관리 (Policy Based Network Management: PBNM) 구조에 프로그래머블 네트워크 기법을 접목한 것으로, 다양한 이기종의 보안 장비를 보안 정책을 통해 관리할 수 있으며, 보안 장비 간 연동을 제공한다. 또한, 미들웨어에서 보안 정책을 실행 가능한 형태로 변환해 줌으로써 관리상의 편이성을 제공하고 정책 서버의 부하를 줄일 수 있다. 본 논문에서는 제안된 구조와 PBNM 구조에서의 정책적용 및 변환시간과 메시지 전달시간을 비교함으로써 프로그래머블 미들웨어가 관리 트래픽의 부하를 줄일 수 있다는 것을 검증하였다.

• 한국음향학회지
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• 제5권3호
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• pp.13-20
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• 1986

본 논문은 신호처리가 가능한 2진 로가리즘 상수를 발생시키기 위한 programmable variable-rate up/down 계수기의 설계를 기술한다. 2진수에 대한 밑수가 2인 로가리즘 계승의 적용은 결 과적으로 오차가 발생한다. log\sub 2\(1+χ)-χ에 의해 정의된 것처럼 log\sub 2\(1+χ)에서의 오차는 직선의 집합으로 갖게된다. 계수기 rate는 직선의 기울기에 비례한다. 그러므로 신호처리가 가능한 2진 로가리즘 상수는 programmable 계수기를 사용함으로써 쉽게 발생될 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.45-48
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• 2001

An programmable current-mode folding and interpolation analog to digital converter (ADC) with programmable interpolator is proposed in this paper. A programmable interpolator is employed not only to vary the resolution of data converter, but also to decrease a power dissipation within the ADC. Because of varying the number of interpolation circuits, resolution is vary from 6 to 10bit. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The experimental result shows the power dissipation from 26 to 87mW with a power supply of 3.3V.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.407-412
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• 1987

A large scale programmable controller is developed which adopts a multiprocessor structure. The developed programmable controller consists of the programmer, the system controller, and the input-output unit. The structure and characteristics of the system controller will be described. The PC has a special hardware scheme to solve the Boolean logic instructions of the sequence control programs. The multiprocessor structure and the special hardware enables, the real time operation and the high speed scanning which is prerequisite to the large scale, programmable controller even for many I/O points.

• Transactions on Electrical and Electronic Materials
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• 제9권6호
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• pp.227-230
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• 2008

Programmable Metallization Cell (PMC) Random Access Memory is based on the electrochemical growth and removal of electrical nanoscale pathways in thin films of solid electrolytes. In this study, we investigated the nature of thin films formed by the photo doping of copper ions into chalcogenide materials for use in programmable metallization cell devices. These devices rely on metal ions transport in the film so produced to create electrically programmable resistance states. The results imply that a Cu-rich phase separates owing to the reaction of Cu with free atoms from chalcogenide materials.

• 대한전기학회논문지
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• 제32권7호
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• pp.254-260
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• 1983

In this paper a basic design procedure for programmable instruments of IEEE-488 BUS system has been discussed by designing a specific programmable frequency counter with its hardware and software. The designed programmable frequency counter has a programmable range switch and a function of the programable number of measurements. It contains five basic functions(Talker. Listener, Source handshake, Accepter handshake and Controller) of a IEEE-488 BUS and the Device-Trigger as a supplimentary function. The hardware has been built along with 6800 MPU and 68488 GPIA, and its software has included initialization, interrupt handler, BI.GET,BO and controller routines, The designed system given in this paper has been successfuly tested via some experiments.