A Design on Novel Architecture Programmable Frequency divider for Integer-N Frequency Synthesizer

Integer-N 주파수 합성기를 위한 새로운 구조의 프로그램어블 주파수 분주기 설계

Frequency divider selects the channel of the frequency synthesizer. General programmable divider has many flip-flops to realize all integer division value and stability problem by using dual modules prescaler. In this paper, a new architecture of programmable divider is proposed and designed to improve these problems. The proposed programmable divider has only thirteen flip-flops. The programmable divider is designed by 0.65${\mu}{\textrm}{m}$ CMOS technology and HSPICE. Operating frequency of the programmable divider is 200MHz with a 3V supply voltage.