• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.183-190
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• 2010

We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.

• Journal of the Korean Society for Precision Engineering
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• v.5 no.3
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• pp.63-70
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• 1988

This paper presents the development of a microcomputer-aided design program for a SISO control system. The program has been written in GWBASIC language which is suitable for Intel 80861 CPU with 640KB memory. By utilizing this program, sampling time, the number of bits for the A/D and D/A converter, and the stability for the digital control system can be determined. To demonstrate the utility of this program, a microcomputer controlled precision temperature control system has been employed as an example.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.282-287
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• 1987

This paper presents the development of a microcomputer-aided design program for a digital control system. The program has been written in GWBASIC language which is suitable for Intel 8086II CPU with 640KB memory. By utilizing this program, sampling time, the number of bits A/D and D/A converter, and the stability for the digital control system carl be determined, To demonstrate the utility of this program, a microcomputer controlled precision temperature control system has been employed as an example.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• Journal of The Korean Society of Integrative Medicine
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• v.1 no.3
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• pp.79-95
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• 2013

Purpose : This study aims to investigate the effect of the Snoezelen and Rehacom programs on improvement of attention and memory, and the effect of the Snoezelen program on stress reduction. Method : This study was targeted at 11 subjects in the Snoezelen experimental group, 11 subjects in the Rehacom group and 11 subjects in the non-experimental group. As the initial evaluation, all the subjects took electroencephalography. Then, the Snoezelen group and Rehacom group did Snoezelen training and Rehacom training, respectively total 12 times(for 20 minutes twice per week for six weeks), but no training was applied to the control group. Three weeks after the training, the interim was carried out, and four weeks after the training, the final evaluation was carried out. Results : Subjects' attention increased to $58.15{\pm}4.96$ from $43.75{\pm}4.69$ during the Snoezelen training, and increased to $49.85{\pm}1.91$ from $43.28{\pm}2.71$ during the Rehacom training, which means the Snoezelen training was more effective in improving attention(P<0.05). Subjects' memory increased to $56.14{\pm}1.26$ from $43.19{\pm}3.46$ during the Snoezelen training, and increased to $50.94{\pm}4.0$ from $43.07{\pm}2.58$ during the Rehacom training. This also implies that the Snoezelen training was more effective in improving memory(P<0.05). Conclusion : Though both of the Snoezelen training and Rehacom training improved attention and memory, the Snoezelen program was more effective, and it also influenced stress resistance and physical arousal.

• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.566-571
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• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.4
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• pp.260-273
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• 2007

The wireless sensor network (WSN) nodes are required to operate for several months with the limited system resource such as memory and power. The hardware platform of WSN has 128Kbyte program memory and 8Kbytes data memory. Also, WSN node is required to operate for several months with the two AA size batteries. The MAC, Network protocol, and small application must be operated in this WSN platform. We look around the problem of memory and power for WSN requirements. Then, we propose a new computing model of system software for WSN node. It is the Atomic Object Model (AOM) with Dual Priority Scheduling. For the verification of model, we design and implement IEEE 802.15.4 MAC protocol with the proposed model.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.117-124
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• 1994

In this pape, we propose a graph-theoretic approach for solving the allocation problem for the synthesis of datapaths based on multiport memories. An efficient algorithm is devised by using the weighted bipartite matching algorithm to assign variables to each port of memory modules. The proposed algorithm assigns program variables into a minimum number of multiport memory modules such that usage of memory elements and interconnection cost can be kept minimal. Experimental results show that the proposed algorithm generates the datapaths with fewer registers in memory modules and less interconnection cost for several benchmarks available from the literatures.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.257-258
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• 1998

To reveal the interconnected brain regions involved in human working memory, their functional connectivity was analyzed using principal component analysis (PCA). rCBF PET scans were peformed on 5 normal volunteers during the verbal and visual working memory tasks and PCA was applied. PCA produced the first principal components related with the increase of the difficulty and the second one which demonstrate the dissociation of verbal and visual memory system.