• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.451-456
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• 2007

In this paper, we regard computer systems as heterogeneous multi-server systems and propose a cumulative fair scheduling scheme that pursues long-term fairness. GPS(generalized processor sharing)-based scheduling algorithms, which are usually employed in single-server systems, distribute available capacity in an instantaneous manner. However, applying them to heterogeneous multi-server systems may cause unfairness, since they may not prevent the accumulation of scheduling delays and the extra capacities are distributed in an instantaneous manner. In our scheme, long-term fairness is pursued by proper distribution of extra capacities while guaranteeing reserved capacities. A reference capacity model to determine the ideal progresses of applications is derived from long-term observations, and the scheduler makes the applications gradually follow the ideal progresses while guaranteeing their reserved capacities. A heuristic scheduling algorithm is proposed and the scheme is examined by simulation.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.4
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• pp.189-198
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• 2015

Most IoT-related approaches have tried to establish the relation by connecting the network between things. The proposed research will present how the pervasive interaction of eco-system formed by touching the objects between humans and things can be recognized on purpose. By collecting and sharing the detected patterns among all kinds of things, we can construct the environment which enables individualized interactions of different objects. To perform the aforementioned, we are going to utilize technical procedures such as event-driven signal processing, pattern matching for signal recognition, and hardware in the loop simulation. We will also aim to implement the prototype of sensor processor based on Arduino MCU, which can be integrated with system using Arduino-Matlab/Simulink hybrid-interoperation environment. In the experiment, we use piezo transducer to detect the vibration or vibrates the surface using acoustic wave, which has specific frequency spectrum and individualized signal shape in terms of time axis. The signal distortion in time and frequency domain is recorded into memory tracer within sensor processor to extract the meaningful pattern by comparing the stored with lookup table(LUT). In this paper, we will contribute the initial prototypes for the acoustic touch processor by using off-the-shelf MCU and the integrated framework based on Matlab/Simulink model to provide the individualization of the touch-sensing for the user on purpose.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1134-1143
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• 2000

We propose a scheduling algorithm, Bandwidth Allocation Scheme (BAS), that guarantees bounded delay in a switching node. It is based on the notion of the GPS (Generalized Processor Sharing) mechanism, which has clarified the concept of fair queueing with a fluid-flow hypothesis of traffic modeling. The main objective of this paper is to determine the session-level weights that define the GPS sewer. The way of introducing and derivation of the so-called system equation' implies the approach we take. With multiple classes of traffic, we define a set of service curves:one for each class. Constrained to the required profiles of individual service curves for delay satisfaction, the sets of weights are determined as a function of both the delay requirements and the traffic parameters. The schedulability test conditions, which are necessary to implement the call admission control, are also derived to ensure the proposed bandwidth allocation scheme' be able to support delay guarantees for all accepted classes of traffic. It is noticeable that the values of weights are tunable rather than fixed in accordance with the varying system status. This feature of adaptability is beneficial towards the enhanced efficiency of bandwidth sharing.

• International Journal of Contents
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• v.13 no.2
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• pp.29-34
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• 2017

Cloud computing is becoming an effective and efficient way of computing resources and computing service integration. Through centralized management of resources and services, cloud computing delivers hosted services over the internet, such that access to shared hardware, software, applications, information, and all resources is elastically provided to the consumer on-demand. The main enabling technology for cloud computing is virtualization. Virtualization software creates a temporarily simulated or extended version of computing and network resources. The objectives of virtualization are as follows: first, to fully utilize the shared resources by applying partitioning and time-sharing; second, to centralize resource management; third, to enhance cloud data center agility and provide the required scalability and elasticity for on-demand capabilities; fourth, to improve testing and running software diagnostics on different operating platforms; and fifth, to improve the portability of applications and workload migration capabilities. One of the key features of cloud computing is elasticity. It enables users to create and remove virtual computing resources dynamically according to the changing demand, but it is not easy to make a decision regarding the right amount of resources. Indeed, proper provisioning of the resources to applications is an important issue in IaaS cloud computing. Most web applications encounter large and fluctuating task requests. In predictable situations, the resources can be provisioned in advance through capacity planning techniques. But in case of unplanned and spike requests, it would be desirable to automatically scale the resources, called auto-scaling, which adjusts the resources allocated to applications based on its need at any given time. This would free the user from the burden of deciding how many resources are necessary each time. In this work, we propose an analytical and efficient VM-level scaling scheme by modeling each VM in a data center as an M/M/1 processor sharing queue. Our proposed VM-level scaling scheme is validated via a numerical experiment.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1082-1091
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• 2000

In Distributed Shared Memory systems, false sharing occurs when two different data items, not shared but accessed by two different processors, are allocated to a single block and is an important factor in degrading system performance. The paper first analyzes shared memory allocation and reference patterns in parallel applications that allocate memory for shared data objects using a dynamic memory allocator. The shared objects are sequentially allocated and generally show different reference patterns. If the objects with the same size are requested successively as many times as the number of processors, each object is referenced by only a particular processor. If the objects with the same size are requested successively much more than the number of processors, two or more successive objects are referenced by only particular processors. On the basis of these analyses, we propose a memory allocation scheme which allocates each object requested by different processors to different pages and evaluate the existing memory allocation techniques for reducing false sharing faults. Our allocation scheme reduces a considerable amount of false sharing faults for some applications with a little additional memory space.

• Journal of Power Electronics
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• v.9 no.3
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• pp.410-417
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• 2009

This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.727-736
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• 2009

In this paper, the $arccos(cos^{-1})$ arithmetic unit for mobile graphics accelerator is designed. The mobile vector graphics applications need tight area, execution time, power dissipation, and accuracy constraints compared to desktop PC applications. The designed processor adopts 2nd-order polynomial approximation scheme based on IEEE floating point data format to satisfy speed and accuracy conditions and reduces area via hardware sharing structure. The arccosine processor consists of 15,280 gates and its estimated operating frequency is about 125Mhz at operating condition of $0.35{\mu}m$ CMOS technology. Because the processor can execute arccosine function within 7 clock cycles, it has about 17 MOPS(million arccos operations per second) execution rate and can be applicable to mobile OpenVG processor. And because of its flexible architecture, it can be applicable to the various transcendental functions such as exponential, trigonometric and logarithmic functions via replacement of ROM and minor hardware modification.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.40-48
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• 2015

This paper presents a processor that performs QR decomposition (QRD) as well as Lattice Reduction (LR) for multiple-input multiple-output (MIMO) systems. By sharing the operations commonly required in QRD and LR, the hardware complexity of the proposed processor is reduced significantly. In addition, the proposed processor is designed based on a multi-cycle architecture so as to reduce the hardware complexity. The proposed processor is implemented with 139k logic gates in a $0.18-{\mu}m$ CMOS process, and its latency is $5{\mu}s$ for $8{\times}8$ MIMO preprocessing both QRD and LR where the operating frequency is 117MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.2
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• pp.62-68
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• 1998

In this paper, we proposed the design of the intelligent traffic control system by using multiprocessor architecture. The inter-processor communication of the architecture is implemented by sharing the serial communication channel. In comparing the conventional traffic control system using single processor architecture, the proposed system uses multiple processors controlling the sub systems such as the signal lights, traffic measurement unit, auxiliary signal lights and peripherals. The main processor controls the communication among the processors and the communication protocol link to the central control center at remote site. The proposed architecture reduces the load and simplifies the program of each processor and enables the real time processing of the add-on features of intelligent traffic control systems. The architecture is implemented and the common channel inter-processor communications and the real time operation is experimented .experimented .