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http://dx.doi.org/10.5573/ieie.2015.52.8.040

A Low-Complexity Processor for Joint QR decomposition and Lattice Reduction for MIMO Systems  

Park, Min-Woo (School of Electronics and Information Engineering, Korea Aerospace University)
Lee, Sang-Woo (School of Electronics and Information Engineering, Korea Aerospace University)
Kim, Tae-Hwan (School of Electronics and Information Engineering, Korea Aerospace University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.52, no.8, 2015 , pp. 40-48 More about this Journal
Abstract
This paper presents a processor that performs QR decomposition (QRD) as well as Lattice Reduction (LR) for multiple-input multiple-output (MIMO) systems. By sharing the operations commonly required in QRD and LR, the hardware complexity of the proposed processor is reduced significantly. In addition, the proposed processor is designed based on a multi-cycle architecture so as to reduce the hardware complexity. The proposed processor is implemented with 139k logic gates in a $0.18-{\mu}m$ CMOS process, and its latency is $5{\mu}s$ for $8{\times}8$ MIMO preprocessing both QRD and LR where the operating frequency is 117MHz.
Keywords
QR decomposition; lattice reduction; low complexity; multi-cycle architecture; latency;
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Times Cited By KSCI : 1  (Citation Analysis)
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