• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 추계학술대회 논문집 학회본부
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• pp.439-442
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• 1990

A powerful general purpose image processing processor is developed using a high-speed DSP chip, TMS320C30. The image processing processor, compatible to the standard VME bus, is composed of VME bus interface unit, video rate image grabbing/coding unit, TMS320C30 interface unit and bank of high-speed SRAMs. The performance is evaluated experimentally with the general image processing algorithms and the results show that the developed processor is capable of high speed image processing.

• 항공우주산업기술동향
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• 제8권2호
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• pp.15-23
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• 2010

본 논문에서는 최근에 개발된 위성 데이터 후처리 시스템의 동향에 대해 기술 하고자 한다. 위성 데이터 후처리 시스템은 위성의 텔레메트리를 분석하고 위성의 상태를 파악하는데 사용되는 시스템으로 빠른 처리속도, 데이터 도시화, 사용의 용이성, 그리고 범용성의 요구사항을 갖는다. 본 논문에서는 이러한 요구사항을 만족시키기 위해 여러 위성 데이터 후처리 시스템이 어떻게 설계되고 구현되었는지를 살펴본다.

• 디지털산업정보학회논문지
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• 제11권2호
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• pp.55-66
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• 2015

In this paper, we design and implement a two-way search algorithm that can provide a customized service through the user with real-time two-way communication using a mobile instant messaging service. Therefore, we design and implement the automative search system which enables delivering message to each user mobile terminal from a plurality of relay mobile terminals by utilizing the mobile instant messenger, not to deliver a message from the main server to the mobile instant messenger user directly. Two-way search system using the mobile instant messenger can be immediately collect the user's response is easy to identify the orientation of each user, and thus can be provided to establish a differentiated service plan. Also, It provides a number of services(text, photos, videos, etc) in real-time information to the user by utilizing the mobile instant messenger service without the need to install a separate application. Experiment results, data processing speed of the category processing way to search for the data of the DB server from a user mobile terminal is about 7.06sec, data processing number per minute is about 13 times. The data processing speed of the instruction processing way is about 3.10sec, data processing number per minute is about 10 times. The data processing speed of the natural language processing way is about 5.13sec, per data processing number per minute is about 7 times. Therefore in category processing way, command processing way and natural language processing way, instruction processing way is the most excellent in aspect of data processing speed, otherwise in aspect of per data processing number per minute, the category processing way is the best method.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2003년도 하계학술대회 논문집
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• pp.110-113
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• 2003

In this paper, the multi-channel high speed data acquisition system is implemented. This high speed signal processing system for 3-D image display is applicable to the manipulation of a medical image processing, multimedia data and various fields of digital image processing. In order to convert the analog signal into digital one, A/D conversion circuit is designed. PCI interface method is designed and implemented, which is capable of transmission a large amount of data to computer. In order to, especially, channel extendibility of images acquisition, bus communication method is selected. By using this bus method, we can interface each module effectively. In this paper, 32-channel A/D conversion and PCI interface system for 3-dimensional and real-time display of the retina image is developed. The 32-channel image acquisition system and high speed data transmission system developed in this paper is applicable to not only medical image processing as 3-D representation of retina image but also various fields of industrial image processing in which the multi-point realtime image acquisition system is needed.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.74-86
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• 2002

본 논문은 결정 궤환 구조를 갖는 차동 위상 검출기의 고속 데이터 처리를 위한 VLSI 구조를 제안한다. 기존 차동 위상 검출 방식의 낮은 BER 성능을 극복하기 위해 DF-DPD, DPD-RGPR, DFDPD-SA 등의 다중 심볼 검출 방식이 제시되었다. 이러한 검출 방식들은 참조 위상으로 사용되는 이전 심볼에서의 잡음 효과를 작게 하기 위하여 검출된 위상을 궤환시키는 구조를 갖고 있다. 하지만, 검출된 위상을 궤환시키는 작용은 데이터 처리 속도를 기존의 차동 위상 검출기보다 느리게 한다. 본 논문에서는 결정 궤환 구조를 갖는 차동 위상 검출기가 기존의 차동 위상 검출 방식처럼 고속으로 데이터를 처리할 수 있는 VLSI 구조를 제안하였다. 제안된 구조는 'M-1' 번째 과정에서 'M' 번째 과정을 미리 계산하는 선계산(pre-calculation) 방식과 'M-1'번째 과정에서 예견 위상들을 궤환시키는 선결정 궤환(pre-decision feedback) 방식을 갖는다. 본 논문에서 제안된 구조는 VHDL(Very-high-speed-IC Hardware Description Language)를 사용하여 RTL(Register Transfer Level)로 구현되었다. 시뮬레이션 결과, 제안된 구조는 고속으로 데이터를 처리함을 확인하였다.

• 디지털산업정보학회논문지
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• 제9권2호
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• pp.63-71
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• 2013

WAVE(Wireless Access for Vehicular Environment) System is a communication technology to monitor system failure and vehicle functions and management services to prevent possible incidents of driving a vehicle. In this paper, we have designed and implemented the mutual message processing through parameter between WME management module that manages WAVE system and MLME that manages the upper layer MAC(Media Access Control) module. Also, in order to verify the validity, we have carried out experiments to compare the speed of data processing by dividing data of 1Mbyte, 2Mbyte, 3Mbyte into the packets of 2KByte and 4KByte. Experiments data processing speed of 2KByte packet were shown about 173.62ms in 1MByte, 2MByte about 352.61ms, 3MByte about 550.13ms and, data processing speed of 4KByte packet, 1MByte approximately 87.56ms, 2MByte about 177.94ms, 3MByte about 277.18ms. Therefore, in WAVE system, the mutual messages processing through the parameters between WME and MLME module can be utilized in the various service of ITS(Intelligent Transportation Systems) depending on the speed of data processing.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.373-374
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• 2008

This paper proposes an architecture for high-speed data processing of the DF-DPD. The DF-DPD have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, an architecture is proposed for high-speed data processing of the differential phase detectors with decision feedback in the DF-DPD.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.118.5-118
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• 2001

This paper describes an image processing method for inspecting the surface outlook of high speed moving plates. Noise free image and a new real time processing methods are required to inspect the surface outlook of the high speed moving plates in real time. It is difficult to get a noise free image due to a signal noise, a light noise and background image in typical industrial factory. Thus, pre-processing techniques should be required to get a good image and produce so many time steps to proceed the image data. The objective of this research is to get image on the surface of the moving plates with a speed of 1m/sec and to detect some defaults on the surface image. So, the pre-processing techniques ...

• 전자공학회논문지B
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• 제30B권2호
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• pp.19-32
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• 1993

This paper suggests the new high-speed input/output techniques in a shared memory multiprocessor system. The high-speed I/O processor which can connect the different kinds of large sized I/O periperal devices, the communication protocol to the main processing units for I/O operations, and the job scheduling scheme are addressed. This paper also introduces the disk cache technique which supports the slow I/O devices comparing with the main processing units. These techniques were implemented in the TICOM system. The performance evaluation statistics were collected and analyzed for the suggested high-speed I/O processing techniques. These statistics show the superiority of the suggested techniques.