Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 1998.10a
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- Pages.1029-1032
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- 1998
A comparative study on the addition architecture of high-speed checksum module
고속 검사합 모듈의 덧셈구조에 관한 비교 연구
Abstract
In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG
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