Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A VLSI Design for High-speed Data Processing of Differential Phase Detectors with Decision Feedback

결정 궤환 구조를 갖는 차동 위상 검출기의 고속 데이터 처리를 위한 VLSI 설계

  • Kim, Chang-Gon (Dept. of Electronic Electrical Computer Engineering, Hanyang University) ;
  • Jeong, Jeong-Hwa (Dept. of Electronic Electrical Computer Engineering, Hanyang University)
  • 김창곤 (한양대학교 전자전기컴퓨터공학부) ;
  • 정정화 (한양대학교 전자전기컴퓨터공학부)
  • Published : 2002.05.01
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Abstract

This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.

본 논문은 결정 궤환 구조를 갖는 차동 위상 검출기의 고속 데이터 처리를 위한 VLSI 구조를 제안한다. 기존 차동 위상 검출 방식의 낮은 BER 성능을 극복하기 위해 DF-DPD, DPD-RGPR, DFDPD-SA 등의 다중 심볼 검출 방식이 제시되었다. 이러한 검출 방식들은 참조 위상으로 사용되는 이전 심볼에서의 잡음 효과를 작게 하기 위하여 검출된 위상을 궤환시키는 구조를 갖고 있다. 하지만, 검출된 위상을 궤환시키는 작용은 데이터 처리 속도를 기존의 차동 위상 검출기보다 느리게 한다. 본 논문에서는 결정 궤환 구조를 갖는 차동 위상 검출기가 기존의 차동 위상 검출 방식처럼 고속으로 데이터를 처리할 수 있는 VLSI 구조를 제안하였다. 제안된 구조는 'M-1' 번째 과정에서 'M' 번째 과정을 미리 계산하는 선계산(pre-calculation) 방식과 'M-1'번째 과정에서 예견 위상들을 궤환시키는 선결정 궤환(pre-decision feedback) 방식을 갖는다. 본 논문에서 제안된 구조는 VHDL(Very-high-speed-IC Hardware Description Language)를 사용하여 RTL(Register Transfer Level)로 구현되었다. 시뮬레이션 결과, 제안된 구조는 고속으로 데이터를 처리함을 확인하였다.

Keywords

References

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