Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2008.06a
- /
- Pages.373-374
- /
- 2008
Architecture for High-speed Data Processing of DF-DPD
DF-DPD의 고속 데이터 처리 구조
-
Kim, Yeong-Sam
(Information and Communication Hanyang University)
;
- Jeong, Jin-Doo (Information and Communication Hanyang University) ;
- Yun, Sang-Hun (Information and Communication Hanyang University) ;
-
Jang, Seong-Hyeon
(Information and Communication Hanyang University)
;
- Jeong, Man-Hee (Information and Communication Hanyang University) ;
- Oh, Dae-Gun (Information and Communication Hanyang University) ;
- Chong, Jong-Wha (Information and Communication Hanyang University)
-
김영삼
(한양대학교 정보통신학부)
;
- 정진두 (한양대학교 정보통신학부) ;
- 윤상훈 (한양대학교 정보통신학부) ;
-
장성현
(한양대학교 정보통신학부)
;
- 정만희 (한양대학교 정보통신학부) ;
- 오대건 (한양대학교 정보통신학부) ;
- 정정화 (한양대학교 정보통신학부)
- Published : 2008.06.18
Abstract
This paper proposes an architecture for high-speed data processing of the DF-DPD. The DF-DPD have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, an architecture is proposed for high-speed data processing of the differential phase detectors with decision feedback in the DF-DPD.
Keywords