• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Journal of IKEEE
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• v.17 no.4
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• pp.484-491
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• 2013

In this paper, we proposed an internal multiband loop embedded monopole antenna for mobile handset that could be used for smart phones. The proposed antenna has a volume of 40 mm(W) ${\times}$ 15 mm(L) ${\times}$ 5 mm(H), ground plane size is 40 mm(W) ${\times}$ 80 mm(L), and covers the GSM900 (Global System for Mobile communications : 880-960 MHz), K-PCS (Korea-Personal Communications Service : 1750-1870 MHz), US-PCS (US Personal Communications Service : 1850-1990 MHz), WCDMA (Wideband Code Division Multiple Access : 1920-2170 MHz), Wibro (2300-2390 MHz), Bluetooth (2400-2483 MHz) and WLAN (Wireless Local Area Network : 2400-2483.5 MHz) bands for VSWR (voltage standing wave ration) less than 3. The proposed loop adding design at middle section of longest branch showed wide impedance bandwidth for the lowest resonance frequency band. The proposed antenna have a lowest resonance frequency band from 738 MHz to 1075 MHz for S11 value of -6dB. A HFSS (High Frequency Structure Simulator) of the Ansys Corporation based on a finite element method is employed to analyze the proposed antenna in the design process and to compare the simulation and experimental results.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.5
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• pp.1-8
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• 2013

This paper implements an integrated vehicle chassis system of ACC(Adaptive Cruise Control) and LKS(Lane Keeping System) based on OSEK OS to vehicle operating system and analyzes its performance through experiments. In recent years active safety and advanced driver assistance system has discussed to improve safety of vehicle. Among the rest, We integrate ACC that controls longitudinal velocity of vehicle and LKS that assists a vehicle in maintaing its driving lane, then implement integrated control system in vehicle. Implemented control system uses OSEK/VDX proposed standard, which is aiming at reusability and safety of software for vehicle and removal hardware dependence of application software. Redesigned control system based on OSEK OS, which is supported by OSEK/VDX, can manage real-time task, process interrupt and manage shared resource. We show by results performed EILS(ECU-In-the-Loop Simulation) that OSEK OS-based integrated controller of ACC and LKS is equivalent conventional integrated controller of ACC and LKS.

• Transactions on Electrical and Electronic Materials
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• v.13 no.6
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• pp.273-277
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• 2012

The vacuum drying process for drying of paper in current transformers was modeled with an aim to develop an understanding of the drying mechanism involved and also to predict the water collection rates. A molecular as well as macroscopic approach was adopted for the prediction of drying rate. Ficks law of diffusion was adopted for the prediction of drying rates at macroscopic levels. A steady state and dynamic mass transfer simulation was performed. The bulk diffusion coefficient was calculated using weight loss experiments. The accuracy of the solution was a strong function of the relation developed to determine the equilibrium moisture content. The actually observed diffusion constant was also important to predict the plant water removal rate. Thermo gravimetric studies helped in calculating the diffusion constant. In addition, simulation studies revealed the formation of perpetual moisture traps (loops) inside the CT. These loops can only be broken by changing the temperature or pressure of the system. The change in temperature or pressure changes the kinetic or potential energy of the effusing vapor resulting in breaking of the loop. The cycle was developed based on this mechanism. Additionally, simulation studies also revealed that the actual mechanism of moisture diffusion in CT's is by surface jumps initiated by surface diffusion balanced against the surrounding pressure. Every subsequent step in the cycle was to break such loops. The effect of change in drying time on the electrical properties of the insulation was also assessed. The measurement of capacitance at the rated voltage and one third of the rated voltage demonstrated that the capacitance change is within the acceptance limit. Hence, the new cycle does not affect the electrical performance of the CT.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.2 s.95
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• pp.104-115
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• 1999

Cutting process, in general, is a closed-loop system consisting of structural dynamics and cutting dynamics, with the cutting forces and the relative displacements between tool and workpiece being the associated variables. There have been a number of works on modeling the cutting process of endmilling, most of which assumed that either one of the tool or workpiece be negligible in tis displacement. In this paper, the relative displacement between tool and workpiece was considered. The proposed model used experimental modal analysis for structural dynamics and an instantaneous uncut chip thickness model for cutting dynamics. Simulation of the model, a time varying cutting system, was performed using 4th order Runge-Kutta method. Subsequent simulation results were utilized to predict chatter over a variety of experiments in slotting operation, showing good agreement.

• ETRI Journal
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• v.41 no.3
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.47-52
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• 2010

In this paper, a phase-locked loop with a self-noise suppressing voltage controlled oscillator to improve a phase noise characteristic has been proposed. The magnitude of the proposed transfer function is maximum 25dB lower than that of a conventional transfer function around a bandwidth. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.395-400
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• 2015

Obtaining the parameters for PID controllers based on limit cycle information for the process in a relay controlled feedback loop has become an accepted practical procedure. If the form of the plant transfer function is known, exact expressions for the limit cycle frequency and amplitude can be derived so that their measurements, assumed error free, can be used to calculate the true parameter value. In the literature, parameter estimation for an assumed form of the plant transfer function has generally been considered for disturbance free cases, except a recently published work of the author. In this paper additional simulation results are reported on exact parameter estimation from relay autotuning under static load disturbances.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.368-371
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• 2003

A new accurate and reliable human-in-the-loop control by artificial neural network (ANN) for human assistance robot was proposed in this paper. The principle of human-in-the-loop control by ANN was explained including the system architecture of human assistance robot control the design of the controller the control process as well as the switching of the different control patterns. Based on the proposed method, the control of meal assistance robot was implemented. In the controller of meal assistance robote a feedforward ANN controller was designed for the accurate position control. For safety a feedback ANN forcefree control was installed in the meal assistance robot. Both controllers have taken fully into account the influence of human arm upon the meal assistance robote and they can be switched smoothly based on the external force induced by the challenged person arm. By the experimental and simulation work of this method for an actual meal assistance robote the effectiveness of the proposed method was verified.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.