• Title/Summary/Keyword: power transistor

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Characteristics of Sputtering Mo Doped Carbon Films and the Application as the Gate Electrode in Organic Thin Film Transistor (스퍼터링 Mo 도핑 탄소박막의 특성과 유기박막트랜지스터의 게이트 전극으로 응용)

  • Kim, Young Gon;Park, Yong Seob
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.1
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    • pp.23-26
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    • 2017
  • Mo doped carbon (C:Mo) thin films were fabricated with various Mo target power densities by unbalanced magnetron sputtering (UBM). The effects of target power density on the surface, structural, and electrical properties of C:Mo films were investigated. UBM sputtered C:Mo thin films exhibited smooth and uniform surfaces. However, the rms surface roughness of C:Mo films were increased with the increase of target power density. Also, the resistivity value of C:Mo film as electrical properties was decreased with the increase of target power density. From the performance of organic thin filml transistor using conductive C:Mo gate electrode, the carrier mobility, threshold voltage, and on/off ratio of drain current (Ion/Ioff) showed $0.16cm^2/V{\cdot}s$, -6.0 V, and $7.7{\times}10^4$, respectively.

High-Frequency PSR-Enhanced LDO regulator Using Direct Compensation Transistor (직접 보상 트랜지스터를 사용하는 고주파 PSR 개선 LDO 레귤레이터)

  • Yun, Yeong Ho;Kim, Daejeong;Mo, Hyunsun
    • Journal of IKEEE
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    • v.23 no.2
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    • pp.722-726
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    • 2019
  • In this paper, we propose a low drop-out (LDO) regulator with improved power-supply rejection (PSR) characteristics in the high frequency region. In particular, an NMOS transistor with a high output resistance is added as a compensation circuit to offset the high frequency noise passing through the finite output resistance of the PMOS power switch. The elimination of power supply noise by the compensating transistor was explained analytically and presented as the direction for further improvement. The circuit was fabricated in a $0.35-{\mu}m$ standard CMOS process and Specter simulations were carried out to confirm the PSR improvement of 26 dB compared to the conventional LDO regulator at 10 MHz.

Efficiency Improvement of HBT Class E Power Amplifier by Tuning-out Input Capacitance

  • Kim, Ki-Young;Kim, Ji-Hoon;Park, Chul-Soon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.4
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    • pp.274-280
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    • 2007
  • This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

The Effects of ${\gamma}-rays$ on Power Devices

  • Lho, Young-Hwan;Kim, Ki-Yup;Cho, Kyoung-Y.
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2287-2290
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    • 2003
  • The electrical characteristics of power devices such as BJT (Bipolar Junction Transistor), and MOSFET (Metal Oxide Field Effect Transistor), etc, are altered due to impinging photon radiation and temperature in the nuclear or the space environment. In this paper, BJT and MOSFET are the two devices subjected to ${\gamma}$ radiation. In the case of BJT, the current gain (${\beta}$) and the collector to Emiter breakdown voltage ($V_{CEO}$) are the two main parameters considered. When it was subjected to ${\gamma}$ rays, the ${\beta}$ decreases as the dose level increases, whereas, $V_{CEO}$ gradually increases as the dose level increases. In the case of MOSFET, the threshold voltage is decreasing as the dose level increases. Here it has been observed the decent rate is an increasing function of the threshold voltage. The on-resistance does not change with respect to the dose. Both the devices recover back the original specification after the annealing is finished. No permanent damage has been occurred.

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Fabrication of Superconducting Flux Flow Transistor using Plasma etching (플라즈마 식각을 이용한 초전도 자속 흐름 트랜지스터 제작)

  • 강형곤;임성훈;고석철;한윤봉;한병성
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.74-77
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    • 2002
  • The channel of the superconducting Flux Flow Transistor has been fabricated with plasma etching method using ICP. The ICP conditions were 700 W of ICP power, 150 W of rf chuck power, 5 mTorr of the pressure in chamber and 1:1 of Ar : Cl$_2$, respectively. The channel etched by plasma gas showed superconducting characteristics of over 77 K and superior surface morphology. The critical current of SFFT was altered by varying the external applied current. As the external applied current increased from 0 to 12 mA, the critical current decreased from 28 to 22 mA. Then the obtained r$\sub$m/ values were smaller than 0.1Ω at a bias current of 40 mA. The current gain was about 0.5. Output resistance was below 0.2 Ω.

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A Study on Parameters for Design of IGBT (IGBT 설계 Parameter 연구)

  • Lho, Young-Hwan;Lee, Sang-Yong;Kim, Yoon-Ho
    • Proceedings of the KSR Conference
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    • 2009.05a
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    • pp.1943-1950
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    • 2009
  • The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

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Superconducting Flux flow Transistor using Plasma Etching (플라즈마 식각을 이용한 초전도 자속 흐름 트랜지스터)

  • 강형곤;고석철;최명호;한윤봉;한병성
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.5
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    • pp.424-428
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    • 2003
  • The channel of a superconducting flux flow transistor has been fabricated with plasma etching method using a inductively coupled plasma etching. The ICP conditions then were ICP Power of 450 W, rf chuck power of 150 W, the pressure in chamber of 5 mTorr, and Ar : Cl$_2$=1:1. Especially, over the 5 mTorr, the superconducting thin films were not etched. The channel etched by plasma gas showed the critical temperature over 85 K. The critical current of the SFFT was altered by varying the external applied current. As the external applied current increased from 0 to 12 mA, the critical current decreased from 28 to 22 mA. Then the obtained trans-resistance value was smaller than 0.1 $\Omega$ at a bias current of 40 mA.

A Study on the Single-Stage AC/DC PFC TTFC(TWO-Transistor Forward Converter) (단일전력단 AC/DC PFC TTFC(Two-Transistor Forward Converter)에 관한 연구)

  • Bae, Jin-Yong;Kim, Yong;Kim, Pill-Soo;Cho, Kyu-Man;Choi, Geun-Soo
    • Proceedings of the KIEE Conference
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    • 2005.07b
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    • pp.1432-1434
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    • 2005
  • Single-stage converters are simpler and less expensive than convention two-stage converters. It can be a challenge, however, to design single-stage converters to satisfy certain key criteria such as input power factor, primary-side do bus voltage, and output voltage ripple. This is especially true for higher power single-stage AC/DC TTFC(Two-Transistor Forward Converter).

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Study on Modeling of GaN Power FET (GaN Power FET 모델링에 관한 연구)

  • Kang, Ey-Goo;Chung, Hun-Suk;Kim, Beum-Jun;Lee, Young-Hun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.51-51
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    • 2009
  • In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340V breakdown voltage. The channel thickness was 3um and the channel doping concentration is 1e17cm-3. And we carried out thermal characteristics, too.

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A Capacitor-less Low Dropout Regulator for Enhanced Power Supply Rejection

  • Yun, Seong Jin;Kim, Jeong Seok;Jeong, Taikyeong Ted.;Kim, Yong Sin
    • IEIE Transactions on Smart Processing and Computing
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    • v.4 no.3
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    • pp.152-157
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    • 2015
  • Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.