• Journal of Satellite, Information and Communications
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• 제11권3호
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• pp.114-118
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• 2016

In this paper, we present the advanced open collector circuit, interface circuit between aerospace electronics. Satellite is composed of a number of electronics, which were provided from various manufacturers. Each company manufactured its own electronics for satellite using its heritage and requirements for their electronics. Therefore each electronics may use different internal supplies. It make a problem between electronics because the supply is different from other electronics, such as the increasing of power dissipation because of the static current and the mismatch of interface voltage, the offset. Proposed circuit can reduce the static current and rising time, and also decrease the useless power dissipation caused by the static current for open collector circuit

• Journal of Advanced Marine Engineering and Technology
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• 제39권8호
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• pp.801-806
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• 2015

The experimental analysis of a crevice-type vapor chamber heat pipe (CVCHP) is investigated. The heat source of the CVCHP is a high-power light-emitting diode (LED). The CVCHP, which exhibits a bubble pumping effect, is used for heat dissipation in a high-heat-flux system. The working fluid is R-141b, and its charging ratio was set at 60 vol.% of the vapor chamber in a heat pipe. The total thermal conductivity of the falling-liquid-film-type model, which was a modified model, was 24% larger than that of the conventional model in the LED package. Flow visualization results indicated that bubbles grew larger as they combined. These combined bubbles pushed the working fluid to the top, partially wetting the heat-transfer area. The thermal resistance between the vapor chamber and tube in the modified design decreased by approximately 32%. The overall results demonstrated the better heat dissipation upon cooling of the high-power LED package.

• ETRI Journal
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• 제24권6호
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• pp.473-476
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• 2002

This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don't-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.813-816
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• 2005

In last several years, the need for the right of privacy and mobile banking has increased. The RSA system is one of the most widely used public key cryptography systems, and its core arithmetic operation IS modular multiplication. P. L. Montgomery proposed a very efficient modular multiplication technique that is well suited to hardware implementation. In this paper, the montgomery modular multiplication algorithms(CIOS, SOS, FIOS) , developed by Cetin Kaya Koc, is presented and implemented using radix-16 and Altera FPGA. Also, we undertake comparisons of power dissipation using Quatrus II PowerPlay Power Analyzer.

• Journal of the Korean Institute of Intelligent Systems
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• 제10권5호
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• pp.478-486
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• 2000

This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.

• The Magazine of the Society of Air-Conditioning and Refrigerating Engineers of Korea
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• 제17권2호
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• pp.131-139
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• 1988

The thermoacoustic oscillation induced in an air column with variable cross section area is investigated theoretically and experimentally. The onset condition of the oscillation is derived by equating the acoustic power production to the power dissipation. The power production at the heater is predicted by using the efficiency factor obtained by heat transfer analysis for a single wire in a uniform cross flow and considering the interference between heater wires. The power dissipation is estimated by measuring the attenuating coefficient from the pressure decay curve. The theoretical prediction to the onset condition of the oscillation is confirmed experimentally. The effect of the variation of the column cross section area on the onset condition is presented.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 한국방송공학회 2009년도 IWAIT
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

• Proceedings of the KIEE Conference
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• 대한전기학회 1999년도 하계학술대회 논문집 E
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• pp.2101-2103
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• 1999

The insulation condition of stator windings was measured by dissipation factor($tan{\delta}$) test in the six high voltage motors(rated 6.6kV) which had been in service for two years. The ${\Delta}tan{\delta}$ of motor D and E was higher than that of the rest motors. The specimens were drawn out from stator windings of the high voltage motor and their were analyzed using scanning electron microscope (SEM). SEM result shows that large voids are present in the interface both turn insulation and groundwall insulation.

• Journal of the Korea Institute of Military Science and Technology
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• 제10권2호
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• pp.152-159
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• 2007

This paper describes the design, fabrication, and measurement of ROIC(ReadOut Integrated Circuit) for $320{\times}256$ IRFPA(InfraRed Focal Plane Array). A ROIC plays an important role that transfer photocurrent generated in a detector device to thermal image system. Recently, the high performance and low power ROIC adding various functions is being required. According to this requirement, the design of ROIC focuses on 7MHz or more pixel rate, low power dissipation, anti-blooming, multi-channel output mode, image reversal, various windowing, and frame CDS(Correlated Double Sampling). The designed ROIC was fabricated using $0.6{\mu}m$ double-poly triple-metal Si CMOS process. ROIC function factors work normally, and the power dissipation of ROIC is 33mW and 90.5mW at 7.5MHz pixel rate in the 1-channel and 4-channel operation, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제56권11호
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• pp.2017-2022
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• 2007

In a memory, most power is dissipated in line of high capacitance such as decoder lines, word lines, and bit * lines. The decoder size as well as the parastic capacitances of the bit-line are going to reduce, if ROM core size reduces. This paper proposes to reduce a mathod of power dissipation for reducing ROM core size. Design result of ROM used in FFT[2], proposed method lead to up to 40.6%, 42.12%, 37.82% reduction in area, power consumption and number of Tr. respectively compared with previous method.