• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.526-529
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67ns access time for a 3-V powr supply. It was achieved using the sense amplifier with multiple point sensing scheme and high speed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5.mu.m double-polysilicon and triplemetal CMOS process technology. A die size is 1.78mm*2.13mm.

• 대한전자공학회논문지SD
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• 제38권2호
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• pp.51-51
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• 2001

본 논문은 디지털 순서회로 설계시 상태할당 알고리즘 개발에 관한 연구로, 동적 소비전력을 감소시키기 위하여 상태변수의 변화를 최소로 하는 코드를 할당하여 상태코드가 변화하는 스위칭횟수를 줄이도록 하였다. 상태를 할당하는데는 Markov의 확률함수를 이용하여 hamming거리가 최소가 되도록 상태 천이도에서 각 상태를 연결하는 edge에 weight를 정의한 다음, 가중치를 이용하여 각 상태들간의 연결성을 고려하여 인접한 상태들간에는 가능한 적은 비트 천이를 가지도륵 모든 상태를 반복적으로 찾아 계산하였다. 비트 천이의 정도를 나타내기 위하여 cost 함수로 계산한 결과 순서회로의 종류에 따라 Lakshmikant의 알고리즘보다 최고 57.42%를 감소시킬 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.465-466
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• 2008

This paper shows analysis of digital correction of pipelined ADC. Sub-ADCs have some margin because of digital correction so, it can be reduced bias current for minimizing power dissipation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.763-766
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• 2002

This paper proposes design of new linear bipolar OTAs composed of an hyperbolic function circuit and a triple-tail cell. Two types of the OTAs are presented; one employs a hyperbolic sine circuit and the other contains a hyperbolic cosine circuit. The linear input voltage ranges of the proposed OTAs are wider than that of the conventional triple-tail cell, though the power dissipation is smaller. The results of SPICE simulation show that satisfactory characteristics are obtained.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.164-167
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• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.81-84
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• 2001

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.289-292
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• 2001

A Novel fully-differential bipolar current-controlled current amplifier(CCCA) for electrically tunable circuit design at current-mode signal processing were designed. The CCCA was consisted of fully-differential subtracter and fully-differential current gain amplifier. The simulation result shows that the CCCA has current input impedance of 0.5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100$mutextrm{A}$ to 20 ㎃. The power dissipation is 3 mW.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.357-360
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• 1999

A 20 MHz CMOS continuous low-pass filter using simulated floating inductor consisted of two fully-differential transconductors and a capacitor is presented. The theory of operation is described and simulation results show close agreement between predicted behaviour and experimential performance. Simulation results show that the filter has ripple bandwidth of 22 MHz, pass-band ripple of 0.36 ㏈. and cutoff frequency of 26 MHz at supplay voltage of $\pm$3 V. The power dissipation is 19.2 ㎽.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.287-290
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• 1999

In the transmitter of optical fiber transmission systems, a time-division multiplexer combines several parallel data streams into a single data stream with a high bit rate. In this paper, we design a 2:1 (2-channels) time-division multiplexer using SiGe HBT with emitter size of 2$\times$8${\mu}{\textrm}{m}$$^2$. The operation speed is 10Gbps, the rise and fall times of 20-80% are 34ps and 35ps, respectively and the dissipation of power is 0.86W.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.971-974
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• 1999

A offset compensated class A bipolar second-generation current conveyor (CCII) for high-accuracy current-mode signal processing was proposed. The CCII adopts two diode-connection transistor between voltage input and voltage output to reduce offset voltage. Experiments show that the proposed CCII has offset voltage of 0.05 ㎷, input impedance of 2 Ω and the 3-㏈ cutoff frequency of 30 MHz when used a voltage amplifier. The power dissipation is 6 ㎷.