• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• ETRI Journal
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• 제30권5호
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• ETRI Journal
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• 제30권3호
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• pp.347-354
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• 2008

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 ${\mu}m$ EEPROM process. Power dissipation is 32.78 ${\mu}W$ in the read cycle and 78.05 ${\mu}W$ in the write cycle. The layout size is 449.3 ${\mu}m$ ${\times}$ 480.67 ${\mu}m$.

• 한국소음진동공학회논문집
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• 제14권12호
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• pp.1207-1222
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• 2004

In this paper, the explicit equations on the power consumption and sensitivity ratio of VCM-type actuator for disk drive are proposed. The power consumption and sensitivity ratio is derived in frequency domain. The power consumption during the track following of the actuator can be described well in frequency domain and it can be used to calculate the total power dissipation of the actuator which is needed to compensate the tracking and focusing errors. Also, the sensitivity ratio of an actuator is derived by using the reference servo of a disk drive and will be used to optimally obtain the performances of the actuator. This sensitivity ratio can persuasively explain the basis of the target performances of the actuator in the considerations of the reference servo. The usefulness of the proposed equations for the sensitivity ratio and power consumption of an actuator is shown by a lot of simulations. In the near future, we will verify the simulation results by experiments.

• 한국의류학회지
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• 제36권9호
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• pp.916-927
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• 2012

In the $21^{st}$ century, woman leaders are able to influence society through improved social status and economic power. From 1980-1990 there was a rapid global social development of feminism and improved media perceptions. The progression of this process is reflected by female characters in feminism films that included a new dress style. The power suit emerged in the U.S.A of the 1980s, as a dress code that showed the workplace uniform of a professional woman and spread to Korea as an influential style. This study defines the different and similar aspects in the development of women's position and the role involved in a structural background through a comparison of the socio-cultural meaning of the power suit expressed in American and Korean feminism films. For analysis, this study chose American films in the 1980s and Korean films in 1990s that fulfilled elements about feminism films. Subsequently in American feminism films, the power suit expressed an equal authority with men, strategic use of femininity according to task type, and a dissipation of symbolic effects like a rich look. In Korean feminism films, the power suit expressed an end of femininity like female transvestite, independent female images with the masculinization of appearance, and a mix of new and traditional styles.

• 전력전자학회논문지
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• 제25권5호
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• 한국인터넷방송통신학회논문지
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• 제22권5호
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• pp.99-103
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• 2022

밀리미터파 추적 레이더는 다양한 환경조건에서 운용하므로 입력전압의 큰 변동에도 안정적인 출력전원을 공급하는 전원공급기가 필요하며, 송수신기에 고품질의 전원공급을 위해 낮은 잡음레벨 특성을 가져야 한다. 본 논문에서는 Ka-대역 추적 레이더에 적용하기 위한 최대 출력 727 W급의 소형 전원공급기 설계 및 구현방안에 대해 기술한다. 전압안정도 및 효율 요구사항을 충족하기 위해 buck 타입의 DC-DC 컨버터의 윗면이 전원공급기의 커버와 맞닿게 배치하여 방열효율을 극대화하였다. 최대 부하 조건에서 시스템 효율 88.4 %, 전압정밀도 ±2 %, 잡음레벨은 전압값의 1 % 이내임을 확인하였다.

• The Journal of the Acoustical Society of Korea
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• 제18권3E호
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• pp.44-48
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• 1999

The CMOS four-quadrant analog multiplier for low-voltage low-power applications are presented in this thesis. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building block. SPICE simulations are carried out to examine the performances of the designed multiplier. Simulation results are obtained by 0.6㎛ CMOS parameters with 2V power supply. The basic configuration of the multiplier is the CMOS Gilbert cell with two LV composite transistors. The linear input range of the multiplier is over ±0.4V with a linearity error of less than 1.3%. The measured -3dB bandwidth is 288MHz and the power dissipation is 255 ㎼.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.321-324
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• 2004

In this paper, attenuation characteristics of silica-based variable optical attenuator (VOA) with heat insulating structures are investigated by variations of structural parameters and heating power at wavelength 1.55${\mu}m$. The characteristics of power dissipation and attenuation at this VOA was optimized in terms of heating insulating width, under-cladding height and over-cladding height. The optimized maximum attenuation of this VOA was achieved about 31dB at heating power 150mW.