• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.89-93
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• 2018

Ceramic substrates applied to power modules of electric vehicles are required to have properties of high thermal conductivity, high electrical insulation, low thermal expansion coefficient and resistance to abrupt temperature change due to high power applied by driving power. Aluminum nitride and silicon nitride, which are applied to heat dissipation, are considered as materials meeting their needs. Therefore, in this paper, the properties of aluminum nitride and silicon nitride as radiator plate materials were compared through a commercial analysis program. As a result, when the process of applying heat of the same condition to aluminum nitride was implemented by simulation, the silicon nitride exhibited superior impact resistance and stress resistance due to less stress and warping. In terms of thermal conductivity, aluminum nitride has superior properties as a heat dissipation material, but silicon nitride is more dominant in terms of reliability.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.10
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• pp.213-220
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• 2020

The power consumption and performance of hardware-based mobile and IoT embedded systems that require high specifications are one of the important issues of these systems. In particular, the problem of excessive power consumption is because it causes a problem of increasing heat generation and shortening the life of the device. In addition, in the same environment, software also needs to perform stable operation in limited power and memory, thereby increasing power consumption of the device. In order to solve these issues, we propose a Low level power improvement via identifying performance dissipation. The proposed method identifies complex modules (especially Cyclomatic complexity, Coupling & Cohesion) through code visualization, and helps to simplify low power code patterning and performance code. Therefore, through this method, it is possible to optimize the quality of the code by reducing power consumption and improving performance.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.62-72
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• 2010

PM OLED is used in many applications as one of the display for the next generation. The most essential problems are the power dissipation and the short life time in applying PM OLED into a commercial application. Many efforts are made in developing the panel and in improving the circuit for expanding the current market wider. The life time in PM OLED is expanded by lessening the power dissipation of the circuit for the magnitude of the driving current is lowered. It is possible to minimize the power dissipation from improving the driving technology. The classical technology, Row-to-Row driving, is that row is selected one by one while applying the column current input individually. The multi-line driving is a new technology which is to select multiple rows simultaneously while applying the column current as a whole. However, the solution of the multi-line driving is NP-complete problem. The efficiency is dependant on the sort of picture and the driving condition. This paper presents the new efficient multi-line driving which is that the multiple lines are selected by applying column current together after grouping the simultaneous driving group applying the gnew efficient muthe coi-line dr coefficient. Bengrouping the several rows which has the higher coi-line dr coefficient, the more efficient driving is realized to present the high quality image and to lessen the power dissipation and to stretch the life time in the PM OLED.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.7-17
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• 2010

In this paper, an innovative low-power SRAM based on 4-transistor latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. Moreover, the design reduces the leakage current in the memory cells. The proposed SRAM has been demonstrated through 16-kbit test chip fabricated in a 0.18-${\mu}m$ CMOS process. It shows 17.5 ns access at 1.8-V supply while consuming dynamic power of $87.6\;{\mu}W/MHz$ (for read cycle) and $70.2\;{\mu}W/MHz$ (for write cycle). Compared with those of the conventional 6-transistor SRAM, it exhibits the power reduction of 30 % (read) and 42 % (write) respectively. Silicon measurement also confirms that the proposed SRAM achieves nearly 64 % reduction in the total standby power dissipation. This novel SRAM might be effective in realizing low-power embedded memory in future mobile applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.594-599
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• 2014

The heat dissipation conditions of high-power 5 watt LEDs-based searchlight modules were optimized with varying LED bar'shape, materials, and ambient temperature. The LED junction temperature was estimated by using Computational Fluid Dynamics simulation. The optimal heat dissipation conditions were found as follows; LED bar' shape: L=80 mm, W=4 mm, t=10 mm, copper material, LED junction temperature of $116.6^{\circ}C$, ambient temperature of $50^{\circ}C$, total mass of 184 g, and shadowing area of $320mm^2$. The difference between the junction temperatures of our fabricated and simulated LEDs-based searchlight modules is about $3^{\circ}C$, which confirms the validity of our thermal simulation results.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1804-1814
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• 2015

In order to explore the characteristics of electrons in DC negative corona discharge, an improved plasma chemical model is presented for the simulation of bar-plate DC corona discharge in dry air. The model is based on plasma hydrodynamics and chemical models in which 12 species are considered. In addition, the photoionization and secondary electron emission effect are also incorporated within the model as well. Based on this model, electron mean energy distribution (EMED), electron density distribution (EDD), generation and dissipation rates of electron at 6 typical time points during a pulse are discussed emphatically. The obtained results show that, the maximum of electron mean energy (EME) appears in field ionization layer which moves towards the anode as time progresses, and its value decreases gradually. Within a pulse process, the electron density (ED) in cathode sheath almost keeps 0, and the maximum of ED appears in the outer layer of the cathode sheath. Among all reactions, R1 and R2 are regarded as the main process of electron proliferation, and R₂₂ plays a dominant role in the dissipation process of electron. The obtained results will provide valuable insights to the physical mechanism of negative corona discharge in air.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.1934-1944
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• 2017

As a key component of high-voltage power conversion system for electric vehicles (EVs), bidirectional DC/DC (Bi-DC/DC) is required to have high efficiency and light weight. Conventional design methods optimize the Bi-DC/DC at the maximum power dissipation point (MPDP). For EVs application, the work condition of the Bi-DC/DC is not strict as the MPDP, where the design method using MPDP may not be optimal during travel of EVs. This paper optimizes the Bi-DC/DC converter targeting efficiency and weight based on the driving cycle. By analyzing the two-phase interleaved Bi-DC/DC for hybrid energy storage systems (HESS) of EVs, its power dissipation is calculated, and an efficiency model is derived. On this basis, weight models of capacitor, inductor and heat sink are built, as well as a dynamic temperature model of heat sink. Based on these models, a method using New European Driving Cycle (NEDC) for optimal design of Bi-DC/DC which simultaneously considered efficiency and weight is proposed. The simulation result shows that compare with conventional optimization methods revealed that the optimization approach based on driving cycle allowed significant weight reduction while meeting the efficiency requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.137-144
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• 2001

In this paper, a state assignment algorithm was proposed to reduce power consumption in control-flow oriented finite state machines. The Markov chain model is used to reduce the switching activities, which closely relate with dynamic power dissipation in VLSI circuits. Based on the Markov probabilistic description model of finite state machines, the hamming distance between the codes of neighbor states was minimized. To express the switching activities, the cost function, which also accounts for the structure of a machine, is used. The proposed state assignment algorithm is tested with Logic Synthesis Benchmarks, and reduced the cost up to 57.42% compared to the Lakshmikant's algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.11
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• pp.737-741
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• 2000

We fabricated resistive superconducting fault current limiters (SFCL) based on YBCO thin films grown on 2-inch diameter $Al_2O_3$ substrates. Two SFCLs with nearly identical properties were connected in series to investigate simultaneous quench. There was a slight difference in the rate of voltage increase between two SFCL units when they were operated independently. This difference resulted in significantly imbalanced power dissipation between the units. This imbalance was removed by connecting a shunt resister to an SFCL in parallel. The appropriate values of shunt resistance were 80 ${\Omega}$ at 75 $V_rms$ and 110 ${\Omega}$ at 120 $V_rms$, respectively. Increased power input at high voltages also reduced the initial imbalance in power dissipation, but with increase in film temperature to higher than 200 K.