• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.8
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• pp.5541-5549
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• 2015

This paper introduces a safer and more power efficient heater by using induction heating, to apply to the semiconductor wafer fabrication exhaust gas cleaning system. The exhaust gas cleaning system is currently made with filament heater that generates an endothermic reaction of N2 gas for the removal of moisture. Induction theory, through the bases of theoretical optimization and electronic implementation, is applied in the design of the induction heater specifically for the semiconductor wafer exhaust system. The new induction heating design provides a solution to the issues with the current energy inefficient, unreliable, and unsafe design. A robust and calibrated design of the induction heater is used to optimize the energy consumption. Optimization is based on the calibrated ZVS induction circuit design specified by the resonant frequency of the exhaust pipe. The fail-safe energy limiter embedded in the system uses a voltage regulator through the feedback of the MOSFET control, which allows the system performance to operate within the specification of the N2 Heater unit. A specification and performance comparison from current conventional filament heater is made with the calibrated induction heater design for numerical analysis and the proof of a better design.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.2
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• pp.16-23
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• 2006

This paper presents a novel single-stage high frequency resonant inverter link type DC-DC converter using zero voltage switching with high power-factor. The proposed topology is integrated half-bridge boost rectifier as power factor corrector(PFC) and half-bridge high frequency resonant converter into a single-stage. The input stage of the half-bridge boost rectifier works in discontinuous conduction mode(DCM) with constant duty cycle and variable switching frequency. So that a boost converter makes the line current follow naturally the sinusoidal line voltage waveform. Simulation results have demonstrated the feasibility of the proposed high frequency resonant converter. Characteristics values based on characteristics analysis through circuit analysis is given as basis data in design procedure. Also, experimental results are presented to verify theoretical discussion. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, fluorescent lamp and DC-DC converter etc.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.108-108
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• 2011

최근 에너지 위기와 환경 규제 강화 및 친환경, 녹색성장 등의 이슈가 대두되면서 에너지 절감과 환경보호 분야에 그린 전력반도체 수요가 날로 증가되고 있다. 이러한 그린 전력반도체는 휴대용컴퓨터, 이동통신기기, 휴대폰, 조명, 자동차, 전동자전거, LED조명 등 다양한 종류의 전력소자들이 사용되고 있으며, 전력소자의 수요증가는 IT, NT, BT 등의 융복합기술의 발달로 새로운 분야에 전력소자의 수요로 창출되고 있다. 특히 환경오염을 줄이기 위한 고전압 대전류 전력소자의 에너지 효율을 높이는 연구 개발이 활발히 진행되고 있다. 종래의 전력소자는 평면형의 LDMOS나 VDMOS 기술을 이용한 소전류 주로 제작되어 수십 암페어의 필요한 대전류용으로 사용이 불가능하다. 반면 수직형 전력소자인 트렌치를 이용한 power 소자는 집적도를 증가 시킬 수 있을 뿐만 아니라 대전류 고전압 소자 제작에 유리하다. 특히 평면형 소자에 비해 약 30%이상 칩 면적을 줄일 수 있을 뿐만 아니라 평면형에 비해 on-저항을 낮출 수 있기 때문에 수요가 날로 증가하고 있다. 트렌치 게이트 power MOS의 중요한 게이트 산화막 형성 기술은 트렌치 내부에 균일한 두께의 산화막 형성과 높은 신뢰성을 갖는 게이트 산화막 형성이 매우 중요하다. 본 연구에서는 전력소자를 제조하기 위해 트렌치 기술을 이용하여 수직형 전력소자를 제작하였다. 트렌치형 전력소자는 게이트 산화막을 균일하게 형성하는 것이 매우 중요한 기술이다. 종래의 수평형 소자 제조시 게이트 산화막 형성 후 산화막 두께가 매우 균일하게 성장되지만, 수직형 트렌치 게이트 산화막은 트렌치 내부벽의 결정구조가 다르기 때문에 $1000^{\circ}C$에서 열산화막 성장시 결정구조와 결정면에 따라 약 35% 이상 열산화막 두께가 차이가 난다. 본 연구는 이러한 문제점을 해결하기 위해 트렌치를 형성한 후 트렌치 내부의 결정구조를 변화 및 산화막의 종류와 산화막 형성 방법을 다르게 하여 균일한 게이트 산화막을 성장시켜 산화막의 두께 균일도를 향상시켰다. 그 결과 고밀도의 트렌치 게이트 셀을 제작하여 제작된 트렌치 내부에 동일한 두께의 게이트 산화막을 여러 종류로 산화막을 성장시킨 후 성장된 트렌치 내벽의 산화막의 두께 균일도와 게이트 산화막의 항복전압을 측정한 결과 약 25% 이상 높은 신뢰성을 갖는 게이트 산화막을 형성 할 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.458-461
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• 2015

In this paper 2 types of voltage references and a current reference suitable for low-voltage, low-power circuits are proposed and designed with $0.35{\mu}m\;CMOS$ process. MOS transistors operating in weak inversion and bulk-driven technique are utilized to achieve low-voltage and low-power features. The first voltage reference consumes 1.43uA from a supply voltage of 1.2V while it has a reference voltage of 585mV and a TC(Temperature Coefficient) of $6ppm/^{\circ}C$. The second voltage reference consumes 48pW from a supply voltage of 0.3V while having a reference voltage of 172mV and a TC of $26ppm/^{\circ}C$. The current reference consumes 246nA from a supply voltage of 0.75V with a reference current of 32.6nA and a TC of $262ppm/^{\circ}C$. The performances of the designed references have been verified through simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.8-13
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• 2008

Noise in homogeneous extrinsic semiconductor samples is calculated due to distributed diffusion noise sources. As the length of the device shrinks at a fixed bias voltage, the ac-wise short-circuit noise current shows excess noise as well as thermal noise spectra. This excess noise behaves like a full shot noise when the channel length becomes very small compared with the extrinsic Debye length. For the first time, the analytic formula of the excess noise in extrinsic semiconductors from velocity-fluctuation noise sources is given for finite frequencies. This formula shows the interplay between transit time, dielectric relaxation time, and velocity relaxation time in determining the terminal noise current as well as the carrier density fluctuation. As frequency increases, the power spectral density of the excess noise rolls off. This formula sheds light on noise in nanoscale MOSFETs where quasi-ballistic transport plays an important role in carrier transport and noise.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.1-8
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• 2009

We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• Journal of Industrial Technology
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• v.40 no.1
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• pp.13-18
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• 2020

Lithium-ion batteries have a small volume, light weight and high energy density, maximizing the utilization of mobile devices. It is widely used for various purposes such as electric bicycles and scooters (e-Mobility), mass energy storage (ESS), and electric and hybrid vehicles. To date, lithium-ion batteries have grown to focus on increasing energy density and reducing production costs in line with the required capacity. However, the research and development level of lithium-ion batteries seems to have reached the limit in terms of energy density. In addition, the charging time is an important factor for using lithium-ion batteries. Therefore, it was urgent to develop a high-speed charger to shorten the charging time. In this thesis, a discharger was fabricated to evaluate the capacity and characteristics of Li-ion battery pack which can be used for e-mobility. To achieve this, a smart discharger is designed with a combination of active load, current sensor, and temperature sensor. To carry out this thesis, an active load switching using sensor control circuit, signal processing circuit, and FET was designed and manufactured as hardware with the characteristics of active discharger. And as software for controlling the hardware of the active discharger, a Raspberry Pi control device and a touch screen program were designed. The developed discharger is designed to change the 600W capacity battery in the form of active load.

• Journal of Sensor Science and Technology
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• v.4 no.2
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• pp.7-13
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• 1995

A new FET type semiconductor pressure sensor (PSFET : pressure sensitive field effect transistor) was fabricated and its operational characteristics were investigated. A ZnO thin film as a piezoelectric layer, $5000{\AA}$ thick, was deposited on a gate oxide of FET by RF magnetron sputtering. The deposition conditions to obtain a c-axis poling structure were substrate temperature of $300^{\circ}C$, RF power of 140watt, and working pressure of 5mtorr in Ar ambience. The fabricated PSFET device showed good linearity and stability in the applied pressure range($1{\times}10^{5}\;Pa{\sim}4{\times}10^{5}\;Pa$).

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.8-15
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• 2003

In this paper, the issue of the differential ring oscillator in designing low phase noise is linearity improvement of delay cell's load resistor. A novel differential delay cell that improves on the Maneatis load is proposed. The linearity improvement of load resistor results in lower phase noise in ring oscillator. For comparison of the phase noise characteristics, Ali Hajimiri's phase noise model is used. In order to have a low ISF(impulse sensitivity function), it is important to have a symmetry between rise time and fall time of oscillation waveform. The ISF value of ing oscillator based on the proposed delay cell is lower than that of the existing ring oscillators. Due to this result, the phase noise is improved by 2~3dBc/Hz for the same power dissipation and oscillation frequency.