• 대한전자공학회논문지SD
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• 제41권8호
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• pp.31-36
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• 2004

본 논문에서는 UV 처리와 BOE 세정을 이용하여 레이저 어닐링 전의 실리콘 표면에 자연 산화막을 제거하여 다결정 실리콘 TFT의 신뢰성을 향상시키는 방법을 제안하였다. 전처리 공정이 다결정 실리콘의 표면 거칠기에 미치는 영향을 AFM으로 측정하였으며, 다결정 실리콘 TFT의 전기적 특성인 스위칭 특성과 항복특성을 대형 유리기판의 위치와 전처리의 유무에 대해서 조사하였다.

• 전자공학회논문지A
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• 제32A권5호
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• pp.54-59
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• 1995

We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.39-42
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• 2003

Low temperature polysilicon (LTPS) TFT LCOs are in production today at sizes ranging from 0.33" for Viewfinders to 17" for LCD TVs with 21.3" recently demonstrated. Because of their form factor, resolution, brightness and other benefits, LTPS TFT LCD unit shipments, revenues and capacity are expected to grow rapidly, particularly for mobile applications. However, despite the strong outlook, LTPS TFT LCOs are still faced with numerous challenges from a market and technology perspective. LTPS TFT LCD producers were surveyed on which of the current challenges were the most problematic among other questions.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1075-1078
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• 2007

Negative Bias Temperature Instability (NBTI) in Eximer Laser Annealing (ELA) based Low Temperature polysilicon (LTPS) Thin-Film Transistors (TFT) was investigated. Even though NBTI is generally appeared in devices with thin gate oxide, the TFT with gate oxide thickness of 120 nm, relatively thick, also showed NBTI effect and dynamic NBTI effect is dependent on operational frequency.

• 한국전기전자재료학회논문지
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• 제15권11호
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• pp.969-975
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• 2002

Thin film transistors(TFT) were made based on the polycrystalline Si (poly-Si) crystallized by sequential lateral solidification(SLS) method. The electrical characteristics of the devices were analyzed. n-type TFTs did not show a superior characteristics compared to p-type TFTs. We analyzed the causes of the failure by focused ion beam(FIB) analysis and automatic spreading resistance(ASR) measurement, to study the structural integrity and the doping distribution, respectively. FIB showed no structural problems but it revealed a non-intermixed layer in the contact holes between the polysilicon and the aluminum electrode. ASR analyses on poly-Si layer with various doping concentrations and activation temperatures showed that the inadequately doped areas were partially responsible for the inferior behavior of the whole device.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.513-518
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• 2006

An investigation of the transport properties of polysilicon TFTs, using sequential laterally solidified, SLS, material, is presented. This material has a location controlled distribution of grain boundaries, GBs, which makes it particularly useful for the analysis of their influence on the performance of polysilicon TFTs, and to address the issue of the role of spatially localised trapping states. The experimental results were analyzed by using numerical simulations, and the effective medium approximation was compared with a discrete grain model.

• 한국전기전자재료학회논문지
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• 제11권7호
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• pp.522-526
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• 1998

We have fabricated a LDD structured polysilicon thin film transistor with low leakge current and the optimized LDD length has been obtained. The device performance is improved is improved by hydrogen passivation process. The on.off current ratio of poly0Si TFT s with $0.5{\mu}m$ and $1.0{\mu}m$ LDD length is much higher than that of conventional structured device due to the decrease of leakege current. The optimized LDD length may be $0.5{\mu}$ from the experimental data such as on/off current ratio, threshold voltage and hydrogenation effect.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1865-1869
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• 1990

N-Channel polysilicon MOSFETs (W/L=20/1.5, 3, 5.10\ulcorner) were fabricated using RTP (Rapid Thermal Processor) and hydrogen passivation. The N+ source, drain and gate were annealed and recrystallized using RTP at temperature of 1000\ulcorner-1100\ulcorner. But the active areas were not specially crystallized before growing the gate oxide. Without the hydrogen passivarion, excellent transistor characteristics (ON/OFF=5.10**6, S=85MV/DEC, IL=51pA/\ulcorner) were obtained for 1.5\ulcorner MOSFET. Also the transistor characteristics were improved by hydrogen passivation.

• 한국전기전자재료학회논문지
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• 제16권12호
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• pp.1065-1070
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• 2003

HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.128-128
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• 2011

Polysilicon thin-film transistors (poly-Si TFTs)는 능동행렬 액정 표시 소자(AMLCD : Active Matrix Liquid Crystal Display)와 DRAM과 같은 메모리 분야에 폭넓게 적용이 가능하기 때문에 많은 연구가 진행되고 있다. 최근 poly-Si TFTs의 우수한 특성으로 인하여 주변 driving circuits에 직접화가 가능하게 되었다. 또한 디스플레이 LCD 패널에 controller와 메모리와 같은 다 기능의 장치을 직접화 하여 비용의 절감과 소자의 소형화가 가능한 SOP (System on panels)에 연구 또한 진행 되고 있다. 이미 잘 알려진 바와 같이 비휘발성 메모리는 낮은 소비전력과 비휘발성이라는 특성 때문에 이동식 디바이스에 데이터 저장 장치로 많이 사용되고 있다. 하지만 플로팅 타입의 비휘발성 메모리는 제작공정의 문제로 인하여 SOP의 적용에 어려움을 가지고 있다. SONOS 타입의 메모리는 빠른 쓰기/지우기 효율과 긴 데이터 유지 특성을 가지고 있으나 소자의 스케일링 따른 누설전류의 증가와 10년의 데이터 보존 특성을 만족 시킬 수 가 없는 문제가 발생한다. 본 연구에서는 SOP 적용을 위하여 ELA 방법을 통하여 결정화한 poly-Si TFT memory를 SiO2/Si3N4/SiO2 Tunnel barrier와 High-k HfO2과 Al2O3을 Trapping layer와 Blocking layer로 적용, 비휘발성 메모리을 제작하여 전기적 특성을 알아보았다.