• Journal of the Korean Physical Society
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• 제73권9호
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• pp.1329-1333
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• 2018

We investigated the mechanism of mobility enhancement after the dehydrogenation process in polycrystalline silicon (poly-Si) thin films. The dehydrogenation process was performed by using an in-situ CVD chamber in a $N_2$ ambient or an ex-situ furnace in air ambient. We observed that the dehydrogenated poly-Si in a $N_2$ ambient had a lower oxygen concentration than the dehydrogenated poly-Si annealed in an air ambient. The in-situ dehydrogenation increased the (111) preferred orientation of poly-Si and reduced the oxygen concentration in poly-Si thin films, leading to a reduction of the trap density near the valence band. This phenomenon gave rise to an increase of the field-effect mobility of the poly-Si thin film transistor.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.496-498
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• 2005

We reported that high dielectric hafnium oxide nano-film deposited by thermal atomic layer deposition on the poly-silicon film (poly-Si). The poly -Si film was produced by plasma enhanced chemical vapor deposition and excimer laser annealing. We used the hafniu m chloride ($HfCl_4$) and water as the precursors and analyzed the hafnium oxide film by transmission electron microscope and secondary ion mass spectrometer. Hafnium oxide produced by the ALD method showed very good coverage on the rough surface of poly-Si film. While deposited with 200 cycles, these hafnium oxide films revealed a relatively smooth surface and good uniformity, but the cumulative roughness produced by the incomplete reaction was apparent when the amount of deposition cycle increased to 600 cycles.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.67-68
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• 2000

Polycrystalline silicon (poly-Si) thin film transistors (TFT's) employing vertical amorphous silicon (a-Si) offsets have been fabricated without additional photolithography processes. The a-Si offset has been formed utilizing the poly-Si grain growth blocking effect by thin native oxide film during the excimer laser recrystallization of a-Si. The ON current degradation of the new device after 4 hour's electrical stress was reduced by 5 times compared with conventional poly-Si TFT's.

• 한국전기전자재료학회논문지
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• 제20권2호
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• pp.156-161
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• 2007

This paper describes the characteristics of polycrystalline ${\beta}$ or 3C (cubic)-SiC (silicon carbide) thin films heteroepitaxailly grown on Si wafers with thermal oxide. In this work, the poly 3C-SiC film was deposited by APCVD (atmospheric pressure chemical vapor deposition) method using HMDS (hexamethyildisilane: $Si_{2}(CH_{3}_{6})$ single precursor. The deposition was performed under various conditions to determine the optimized growth conditions. The crystallinity of the 3C-SiC thin film was analyzed by XPS (X-ray photoelectron spectroscopy), XRD (X-ray diffraction) and FT-IR (fourier transform-infrared spectometers), respectively. The surface morphology was also observed by AFM (atomic force microscopy) and voids or dislocations between SiC and $SiO_{2}$ were measured by SEM (scanning electron microscope). Finally, depth profiling was invesigated by GDS (glow discharge spectrometer) for component ratios analysis of Si and C according to the grown 3C-SiC film thickness. From these results, the grown poly 3C-SiC thin film is very good crystalline quality, surface like mirror and low defect. Therfore, the poly 3C-SiC thin film is suitable for extreme environment, Bio and RF MEMS applications in conjunction with Si micromaching.

• 전자공학회논문지D
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• 제35D권6호
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• pp.46-53
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• 1998

저온 공정으로 제작되는 다결정 실리콘 박막 트랜지스터의 활성층을 이중 활성층(a-Si/a-SiN/sub x/)으로 제작하는 공정을 제안하고 다결정 실리콘 박막 트랜지스터를 제작하였다. 본 논문에서는 활성층의 아래쪽 실리콘 박막에 약간의 질소기를 첨가한 후 그 위에 순수한 비정질 실리콘 박막을 증착하여 엑시머 레이저의 에너지로 비정질 실리콘 박막을 결정화하여 사용하였다. 이중 활성층 (a-Si/a-SiN/sub x/)의 경우, 하부층의 NH₃/SiH₄ 유속비가 증가함에 따라, 상부 a-Si 층의 결정 성장이 촉진됨을 알 수 있었으나, n/sup +/ poly-SiN/sub x/ 층의 전도도 특성을 고려해 볼 때, NH₃/SiH₄ 유속비는 0.11의 상한치를 가짐을 알 수 있었다. 전계 방출 전류에 영향을 미치는 광학적 밴드갭의 경우, poly-Si 박막에 비해 증가하였으며, NH₃/SiH₄ 유속비가 0.11 이하에서도 0.1eV 정도의 증가를 보여, 이로 인하여 소자 제작시 전계 방출 전류가 억제될 것을 예상할 수 있다.

• 센서학회지
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• 제16권4호
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• pp.259-262
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• 2007

This paper describes the electrical characteristics of polycrystalline (poly) 3C-SiC thin film diodes, in which poly 3C-SiC thin films on n-type and p-type Si wafers, respectively, were deposited by APCVD using HMDS, $H_{2}$, and Ar gas at $1150^{\circ}C$ for 3 hr. The schottky diode with Au/poly 3C-SiC/Si (n-type) structure was fabricated. Its threshold voltage ($V_{bi}$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_{D}$) value were measured as 0.84 V, over 140 V, 61 nm, and $2.7{\times}10^{19}cm^{-3}$, respectively. Moreover, for the good ohmic contact, Al/poly 3C-SiC/Si (n-type) structure was annealed at 300, 400, and $500^{\circ}C$, respectively for 30 min under the vacuum condition of $5.0{\times}10^{-6}$ Torr. Finally, the p-n junction diodes fabricated on the poly 3C-Si/Si (p-type) were obtained like characteristics of single 3CSiC p-n junction diode. Therefore, poly 3C-SiC thin film diodes will be suitable for microsensors in conjunction with Si fabrication technology.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.175-176
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• 2007

This paper describes on the characteristics of Pd thin films deposited on poly-crystalline 3C-SiC buffer layers for microsensors, in which the poly 3C-SiC was grown on Si, $SiO_2$, and AlN substrates, respectively, by APCVD using HMDS, $H_2$, and Ar gas at $1100^{\circ}C$ for 30 min. In this work, a Pd thin film was deposited on the poly 3C-SiC film by RF magnetron sputter. The thickness, uniformity, and quality of these samples were evaluated by SEM. Crystallinity and orientation of the Pd film were analyzed by XRD. Finally, Pd/poly 3C-SiC schottky diodes were fabricated and characterized by current-voltage measurements. From these results, Pd/poly 3C-SiC devices are promising for high temperature hydrogen sensors and other microsensors.

• ETRI Journal
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• 제29권1호
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• pp.45-49
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• 2007

The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly-Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.

• 한국전기전자재료학회논문지
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• 제24권7호
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• pp.525-531
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• 2011

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

• E2M - 전기 전자와 첨단 소재
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• 제11권11호
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• pp.22-27
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• 1998

We have investigated the effect of an ion shower doping of the laser annealed poly-Si films at an elevated substrate temperatures. The substrate temperature was varied from room temperature to 300$^{\circ}C$ when the poly-Si film was doped with phosphorus by a non-mass-separated ion shower. Optical, structural, and electrical characterizations have been performed in order to study the effect of the ion showering doping. The sheet resistance of the doped poly-Si films was decreased from7${\times}$106 $\Omega$/$\square$ to 700 $\Omega$/$\square$ when the substrate temperature was increased from room temperature to 300$^{\circ}C$. This low sheet resistance is due to the fact that the doped film doesn't become amorphous but remains in the polycrystalline phase. The mildly elevated substrate temperature appears to reduce ion damages incurred in poly-Si films during ion-shower doping. Using the ion-shower doping at 250$^{\circ}C$, the field effect mobility of 120 $\textrm{cm}^2$/(v$.$s) has been obtained for the n-channel poly-Si TFTs.