• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.13-20
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• 2003

The model of the transistor saturation current of the BJT for integrated circuits based upon the semiconductor physics is proposed. The method for calculating the doping profile in the base region using process conditions is presented and the method for calculating the base Gummel number of lateral PNP BJT and vertical NPN BJT is proposed. The transistor saturation currents of NPN BJT using 20V and 30V process conditions obtained from the proposed method show an average relative error of 6.7% compared with the measured data and the transistor saturation currents of PNP BJT show an average relative error of 6.0% compared with the measured data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.415-419
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• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.141-144
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• 2002

The method of the analysis of the base Gummel number of the PNP BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of PNP BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.5-8
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• 1998

기존의 바이폴라 논리회로에서 신호변환시 베이스 영역의 소수 캐리어를 빨리 제거 하기 위해서, 베이스 부분의 매몰충을 줄여서 npn트랜지스터의 베이스와 에피충과 기판사이에 병합 pnp 트랜지스터를 생성한 트랜지스터와 게이트 당 전달 지연 시간을 측정하기 위한 링-발진기를 설계, 제작하였다. 게이트의 구조는 수직 npn 트랜지스터와 기판과 병합 pnp 트랜지스터이다. 소자 시뮬레이션의 자료를 얻기 위하여 수직 npn 트랜지스터와 병합 pnp 트랜지스터의 전류-전압 특성을 분석하여 특성 파라미터를 추출하였다. 결과로서 npn 트랜지스터의 에미터의 면적이 기존의 접합넓이에 비해서 상당히 적기 때문에 에미터에서 진성베이스로 유입되는 캐리어와 가장자리 부분으로 유입되는 캐리어가 상대적으로 많기 때문에 이 많은 양은 결국 베이스의 전류가 많이 형성되며, 또 콜렉터의 매몰층이 거의 반으로 줄었기 때문에 콜렉터 전류가 적게 형성되어 이득이 낮아진다. 병합 pnp 트랜지스터는 베이스폭이 크고 농도 분포에서 에미터의 농도와 베이스의 농도 차이가 적기 때문에 전류 이득이 낮아졌다. 게이트를 연결하여 링-발진기를 제작하여 측정한 AC특성의 출력은 정현파로 논리전압의 진폭은 200mV, 최소 전달 지연시간은 211nS이며, 게이트당 최소 전달지연 시간은 7.26nS의 개선된 속도 특성을 얻었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.10
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• pp.889-895
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• 2008

This paper presents a comprehensive mathematical analysis and simulation of trench IGBT with the help of PIN-PNP combinational model. Since trench IGBT is characteristically influenced by PIN diode, it may be almost impossible to analyze the trench IGBT using PNP-MOS modeling methods, even PIN-MOS techniques which neglect the hole current components coming into p-base region. A new PIN-PNP complementary cooperational model is developed in order to make up the drawbacks of existing models. It would allow us to make qualitative analysis as well as simulation about switching and on-state characteristics of 1,700 V trench IGBT. Moreover, if we improve the PIN diode effects through the optimization of trench structure, trench IGBT is expected to be one of the most promising devices in the not only high-voltage but also high speed switching device field.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.151-154
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• 1998

기존의 바이폴라 논리회로에서 신호변환시 베이스 영역의 소수 캐리어를 빨리 제거하기 위해서, 베이스 부분의 매몰층을 줄여서 npn트랜지스터의 베이스와 에피층과 기판사이에 병합 pnp 트랜지스터를 생성한 트랜지스터와 게이트 당 전달 지연 시간을 측정하기 위한 링-발진기를 설계, 제작하였다. 게이트의 구조는 수직 npn 트랜지스터와 기판과 병합 pnp 트랜지스터이다. 결과로서 npn 트랜지스터의 에미터의 면적이 기존의 접합넓이에 비해서 상당히 적기 때문에 에미터에서 진성베이스로 유입되는 캐리어와 가장자리 부분으로 유입되는 캐리어가 상대적으로 많기 때문에 이 많은 양은 결국 베이스의 전류가 많이 헝성되며, 또 콜렉터의 매몰층이 거의 반으로 줄었기 때문에 콜렉터 전류가 적게 형성되어 이득이 낮아진다. 병합 pnp 트랜지스터는 베이스폭이 크고 농도 분포에서 에미터의 농도와 베이스의 농도 차이가 적기 때문에 전류 이득이 낮아졌다. 게이트를 연결하여 링-발진기를 제작하여 측정한 AC특성의 출력은 정현파로 논리전압의 진폭은 200mV, 최소 전달 지연시간은 211nS이며, 게이트당 최소 전달지연 시간은 7.26nS의 개선된 속도 특성을 얻었다.

• Nuclear Engineering and Technology
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• v.54 no.2
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• pp.501-506
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• 2022

Long turn-off time limits high frequency operation of Bipolar Junction Transistors (BJTs). Turn-off time decreases with increases in the recombination rate of minority carriers at switching transients. Fast neutron irradiation on a Si BJT incurs lattice damages owing to the displacement of silicon atoms. The lattice damages increase the recombination rate of injected holes with electrons, and decrease the hole lifetime in the base region of pnp Si BJT. Fast neutrons generated from a beryllium target with 30 MeV protons by an MC-50 cyclotron were irradiated onto pnp Si BJTs in experiment. The experimental results show that the turn-off time, including the storage time and fall time, decreases with increases in fast neutron fluence. Additionally, it is confirmed that the base current increases, and the collector current and base-to-collector current amplification ratio decrease due to fast neutron irradiation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.21-25
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• 1999

In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. In the result, we get amplitude of logic voltage of 200mV, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26ns in AC characteristic output of Ring-Oscillator connected Gate.