• Journal of the Microelectronics and Packaging Society
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• v.27 no.2
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• pp.1-10
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• 2020

The technology and market size of image sensors continue to develop thanks to the release of image sensors that exceed 100 million pixels in 2019 and expansion of black box camera markets for vehicles in addition to existing mobile applications. We review the technology flow of image sensors that have been constantly evolving for 40 years since Hitachi launched a 200,000-pixel image sensor in 1979. Although CCD has made inroads into image sensor market for a while based on good picture quality, CMOS image sensor (CIS) with active pixels has made inroads into the market as semiconductor technology continues to develop, since the electrons generated by the incident light are converted to the electric signals in the pixel, and the power consumption is low. CIS image sensors with superior characteristics such as high resolution, high sensitivity, low power consumption, low noise and vivid color continue to be released as the new technologies are incorporated. At present, new types of structures such as Backside Illumination and Isolation Cell have been adopted, with better sensitivity and high S/N ratio. In the future, new photoconductive materials are expected to be adopted as a light absorption part in place of the pn junction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.565-568
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm 6.7$$\times$$10^{-3}$/$^{\circ}C$ and $\pm 8.2$$\times$$10^{-4}$/$^{\circ}C$respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and hip high-temperature operation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.9
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• pp.863-867
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• 2008

In this paper, to increase the light current efficiency of photodiode, we fabricated aluminum-doped zinc oxide(AZO) thin films by RF magnetron sputtering. AZO thin films were deposited at low temperature of 100 $^{\circ}C$ and different RF powers of 50, 100, 150 and 200 W due to selective process technology. Then the AZO thin films were annealed at 400 $^{\circ}C$ for 1 hr in vacuum ambient to increase crystalline. The lowest resistivity of 1.35 ${\times}$ $10^{-3}$ ${\Omega}cm$ and a high transmittance over 90 % were obtained under the conditions of 3 mTorr, 100 'c and 150 W. The optimized AZO thin films were deposited as anti-reflection coating on PN junction of silicon photodiode. It was confirmed by the result of $V_r-I_{ph}$ curve that the efficiency of photodiode with AZO thin film was enhanced 17 % more than commercial photodiode.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.7
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• pp.2565-2569
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• 2010

It was researched the correlation between the Solar cell and the effect of texturing. The samples were textured by using the IPA mixed solution with $HNO_3$, KOH and NaOH. The samples were analyzed by the X-ray Diffraction pattern and Fourier Transform Infrared spectroscopy. The FTIR spectra in the range of 950~1350 $cm^{-1}$ was related to the peak's formation as the bonding structure. The split of peaks means that the inter reaction between the molecular did not activate and then increased the efficiency because of low reflectance as shown the cell treated in NaOH mixed solution.

• Journal of Radiation Industry
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• v.9 no.4
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• pp.167-170
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• 2015

Radioisotope (Nuclear) battery using $^{63}Ni$ was prepared as beta cell. The electroplated $^{63}Ni$ on Ni foil is fabricated, and beta cell and photovoltaic hybrid battery was designed to use at both day and night in space project. A Ni-plating solution is prepared by dissolving metal particles including $^{62}Ni$ and $^{63}Ni$ from neutron irradiation of ($n,{\gamma}$). Electroplating solution of a chloride bath consists on nickel ions in HCl, $H_3BO_3$, and KOH. The deposition was carried out at current density of $10mA\;cm^{-2}$. The prepared beta source was attached on a PN junction and measured I-V properties. The power output at activity of 0.07 mCi and 0.45 mCi were 0.55 pW and 2.69 nW, respectively.

• Journal of information and communication convergence engineering
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• v.17 no.2
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• pp.161-165
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• 2019

In this study, zinc tin oxide (ZTO) thin-film transistors are researched to observe the correlation between the barrier potential and electrical properties. Although much research has been conducted on the electronic radiation from Schottky contacts in semiconductor devices, research on electronic radiation that occurs at voltages above the threshold voltage is lacking. Furthermore, the current phenomena occurring below the threshold voltage need to be studied. Bidirectional transistors exhibit current flows below the threshold voltage, and studying the characteristics of these currents can help understand the problems associated with leakage current. A factor that affects the stability of bidirectional transistors is the potential barrier to the Schottky contact. It has been confirmed that Schottky contacts increase the efficiency of the element in semiconductor devices, by cutting off the leakage current, and that the recombination at the PN junction is closely related to the Schottky contacts. The bidirectional characteristics of the transistors are controlled by the space-charge limiting currents generated by the barrier potentials of the SiOC insulated film. Space-charge limiting currents caused by the tunneling phenomenon or quantum effect are new conduction mechanisms in semiconductors, and are different from the leakage current.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.46-51
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• 2023

We investigated the MoS₂ thin film layer by thermolytic deposition and applied it to the silicon solar cells. MoS₂ thin films were made by two methods of dipping and spin coating of (NH₄)₂MoS₄ precursor solution. We implemented two types of substrates of microtextured and nano-microtextured 6-in. Si pn junction wafers. The fabricated MoS₂ thin film layer was analyzed, and solar cells were fabricated by applying the standard silicon solar cell process. The MoS₂ thin film layer of sulfur-deficient form was deposited on the n-type emitter layer, and electrons, which are minority carriers, were well transported at the interface and exhibited photovoltaic solar cell characteristics. The cell efficiencies were achieved at 5% for microtextured wafers and 2.56% for nano-microtextured wafers.

• Journal of Ceramic Processing Research
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• v.21
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• pp.23-27
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• 2020

The enhanced optical output power of AlGaN/GaN deep ultraviolet light-emitting diodes (UV LEDs) were demonstrated by using the breakdown-induced conductive channels (BICCs). The BICCs could be made by electrical reverse biasing between two adjacent contact pads formed on top p-type layers with a certain distance, causing an electrical breakdown of pn junction and hence a generation of conductive channels. Accordingly, the reflective Ni/Ag/Pt electrodes could be formed simultaneously on the top p-type layer and the other p-type layer with the BICCs, acting as the p- and n-contacts, respectively. The deep UV LEDs fabricated with the BICCs produced the enhanced optical output power by 15 % as compared to the reference LEDs, which were fabricated with the conventional Ti/Al/Ti/Au layers formed on mesa-etched n-type layer. This could be due to the reduced light absorption at the n-contact pads, indicating that the use of BICCs will be very suitable for obtaining better output performance of deep UV emitters.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.